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Physical memory limits for CMEM using the c6a816x EVM?

Lee Holeva
Genius 4615 points

Looking at the memory map given in the EZSDK FAQ has me confused about what the physical address limits for CMEM may be:

http://processors.wiki.ti.com/index.php/EZ_SDK_FAQ

 

I get the impression a particular region has been set aside just for CMEM.  It would help if the actual memory addresses had been included in the diagram.  How is the CMEM area related to the kernel memory map given in the PSP Data Sheet?  For example, if I wanted to allocate a pool of 6 buffers of 400000 bytes, what would the physical address limits be?  I appears that the start address, unlike that given in the examples, cannot be 0x0.

I have U-boot in NAND flash:

My boot args:

setenv bootargs 'console=ttyS2,115200n8 rw mem=166M earlyprintk vram=50M ti816xfb.vram=0:16M,1:16M,2:6M root=/dev/nfs nfsroot=192.168.1.100:/home/lholeva/targetfs,nolock ip=192.168.1.10:192.168.1.100: 192.168.1.100:255.255.255.0:c6a8168:eth0:off'

setenv bootcmd 'tftp 0x81000000 uImage-c6a816x-evm.bin;bootm'

 

  • 0
    TI__Mastermind 25055 points

    Lee,

    We are looking into this and will get back to you soon.

    Regards,
    Marc

  • 0
    TI__Mastermind 18260 points

    Lee,

    Missing from that memory map diagram...

     

     300x200px‎

    ... is the implied base address.  On c6a816x the base address is the start of DDR2/3 memory @ 0x80000000.  The above memory map is implemented by telling Linux to use the top & bottom blocks, and therefore Linux doesn't touch the memory in between.  To tell Linux to use those blocks, you would include two mem= in the u-boot bootargs:
        setenv bootargs ... mem=166MB@0x80000000 mem=768MB@0x90000000
    which assumes that you have at least 1 GB available in DDR2/3 memory.

    The CMEM block is implemented by specifying the physical address start/end and the pool geometry on the cmemk.ko 'insmod' line (or 'modprobe' line), typically contained in a script named loadmodules.sh:
        % insmod cmemk.ko phys_start=0x8a600000 phys_end=0x8b000000 pools=6x400000

    The other blocks in the diagram (DSP, SR1) are specified in the DSP executable memory map.

    The key to all this is telling Linux to not touch those memories in between its two blocks, by way of the two "mem=nn@0xnnnnnnnn.

    CMEM should be able to handle being placed anywhere besides 0.  On the DM365, for example, a 28 KB CMEM block is created at 0x1000, in addition to the bigger block placed somewhere in DDR2.

    Regards,

    - Rob