DM8168 PG2.0: Is DE a must signal for discrete sync catpure (YUV)

Hi Chris,

DE is not must signal on PG2.0x. If DE is not present, Hsync or Hblank signals can be used. When hsync is used, VIP will output horizontal blanking data also as part of active video line. In this case, application will have to remove horizontal blanking data from each line.

Thanks,

Brijesh Jadav

Jadav,

Is there any way in HW side to remove th horizontal blanking data if hsync is used in PG2.0, such as SC?

Hi Chris,

Yes, you can use cropping feature of the scalar or VIP to remove extra horizontal blanking area.

Thx,

Brijesh Jadav

Jadav,

Would you pls kindly advise how to crop by VIP directly (not use SC)?

Hi Chris,

We still don't have support for enabling VIP cropping in the driver. Only cropping in the scalar is supported in the capture driver. We will add this feature in upcoming releases.

Thx,

Brijesh Jadav

Jadav,

As you said, in PG2.0 the VIP port will capture the data in horizontal blanking period.  My customer made own discrete sync timing, which is not standard and only will send data once a time, not continuous. So customer though after the last line finishes, the HSYNC signal will keep inactive and the next Vsync will happen after a log time. So the VIP will still write the data in horizontal blanking and will stop only next Vsync comes.

Is their understanding corrrect? If yes, it seems in PG2.0, customer can't use this mode.

Hi Chris,

I did not get how data and blanking signals are sent on your customer platform.

Basically, hsync also toggles during vsync period. vsync period is typically few lines. During this time, hsync still toggles to mark the start of the lines. In VIP, vsync toggling from low to high marks the start of the new frame and hsync toggling from low to high marks the start of the line. It does not strip off the horizontal blanking area, but it captures it the active video buffer.

thanks,

Brijesh Jadav

Jadav,

Pls find the output to DM8118 timing as attached. There is no hsync in blank period. Would you pls check again if what customer thought is correct? Can we fix this in PG2.1?

Chris,

From the diagram, it looks like they have hld and vld signals, which is nothing but the horizontal valid data signal and vertical valid data signals, These signals clearly tells that where new frame starts and when new line starts, These signals can be considered as hsync and vsync signals with inverse polarity and complete frames can be captured. The data in the blanking area can be cropped in VIP crop module, we now have a support for configuring this cropping module in the VIP capture driver in HDVPSS.32 release.  With this, you can capture complete frame in the memory.

Thanks,

Brijesh Jadav

Hi Chris,

It looks vld signal is very short around 4 pixels. In order to detect the frame correctly, size of vsync should be atleast 5 lines. But this should not look like. Can size of the vld be configurable?

Thanks,

Brijesh Jadav