Changing TVP7002 interface from YUV422 to RGB

Carl Blake

Other Parts Discussed in Thread: TVP7002

I'm trying to change the TVP7002 interface from YUV422 to RGB. I'm taking the original linux files provided in ti-ezsdk_dm816x-evm_5_03_01_15/board-support/linux-2.6.37-psp04.00.01.13.patch2 and slightly modifying them to use RGB. I made the following changes:

arch/arm/mach-omap2/ti81xx_fb.c:

Changed hdvpss_capture_sdev_info[ 0 ].vip_port_cfg.ctrlChanSel from VPS_VIP_CTRL_CHAN_SEL_15_8 to VPS_VIP_CTRL_CHAN_DONT_CARE.

Changed hdvpss_capture_sdev_info[ 0 ].vip_port_cfg.video_capture_mode from VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_EMBEDDED_SYNC to VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_DISCRETE_SYNC_HSYNC_VSYNC. This was necessary because the TVP7002 will not output embedded syncs in 444 or RGB mode.

Changed hdvpss_capture_sdev_info[ 0 ].vip_port_cfg.video_if_mode from VPS_CAPT_VIDEO_IF_MODE_16BIT to VSP_CAPT_VIDEO_IF_MODE_24BIT.

Changed hdvpss_capture_sdev_info[ 0 ].vip_port_cfg.input_data_format from FVID2_DF_YUV422P to FVID2_DF_RGB24_888.

drivers/media/video/tvp7002.c:

Changed default I2c register TVP7002_OUT_FORMATTER from 0x47 to 0x04. This sets the TVP7002 to output RGB 30 bit.

I recompiled the kernel to produce a new uImage file in arch/arm/boot and recompiled the modules. I then copied the uImage file to the tftpboot directory as uImage-dm816x-evm.bin. I then copied tvp7002.ko from drivers/media/video to targetfs/lib/modules/2.6.37/kernel/drivers/media/video. I then reset the evaluation module. Everything booted up into linux without any problems.

After that I tried running the saLoopbackFbdev example program, but the system hangs and I have to reset the board.

What am I missing here?

One thing that I've noticed is that there doesn't seem to be any way to indicate that the data from the TVP7002 is no longer 20 bit YUV422 and is now 30 bit RGB (of course the schematic indicates that only 24 of the 30 bits is actually used). There is a V4L2 value for the media bus that seems to indicate this for 20 bit YUV422 (V4L2_MBUS_FMT_YUYV10_1X20), but there isn't a corresponding value that would indicate 30 bit RGB or 24 bit RGB for that matter.

Help?

Carl

over 13 years ago

0 Carl Blake over 13 years ago

Expert 1160 points

Hello? I haven't received any response to this question yet. Does anybody have any ideas? Is anybody even looking into my question?

Carl

0 HardikShah over 13 years ago in reply to Carl Blake

TI__Mastermind 20245 points

Hi,

I will reply to your question by tomorrow end. Open source TVP7002 driver needs some modification which I am looking into it currently.

Regards,

Hardik Shah

0 Carl Blake over 13 years ago in reply to HardikShah

Expert 1160 points

Thank you. That's all I needed to know. I was just worried that my question got lost in the mists of time. I'll be off tomorrow and won't be back until tuesday, so I won't be able to respond until then. I really appreciate your help.

Have a merry Christmas.

Carl

0 Carl Blake over 13 years ago in reply to HardikShah

Expert 1160 points

Hardik,

Hope you had a good Christmas.

I was wondering if you had discovered anything about my question yet. Do you know what kind of modification to the TVP7002 driver needs to be done to get it to work at RGB 24 bit yet?

Thanks.

Carl

0 HardikShah over 13 years ago in reply to Carl Blake

TI__Mastermind 20245 points

Hi,

Regarding discrete sync, DM81xx HDVPSS VIP capture, There is a limitation of VIP capture port that

The VIP port requires that the ACTVID signal is active for all lines of the incoming data, including the vertical blanking region. The vertical blanking region, itself, is not
written to memory. So please make sure that you configure TVP7002 such that ACTVID is active during vertical blanking also.

Regards,

Hardik Shah

0 Carl Blake over 13 years ago in reply to HardikShah

Expert 1160 points

Hardik,

I'm a little confused. I've read carefully through the schematics and the data sheets and I'm not certain what signal you're referring to as the ACTVID signal. Do you mean the DE signal? There is an AVID signal associated with the video output, but there doesn't appear to be an ACTVID signal associated with either of the video input ports. The DE signal is a data enable signal output by the TVP7002, so I can only assume that is what you mean.

For my purposes I'm guessing that I need to make certain that the TVP7002 is outputting a correct signal on its data enable output. Is this right? According to the schematics the TVP7002's FID output is tied (eventually) to VIP0's DE signal. This means I need to make certain that I can set the TVP7002's FID output to be a DE signal. According to the TVP7002 data sheet I'll need to change the TVP7002's MISC_CTL_2 register bits 6-4 (0x17) from 000 to 001. I'll try it and let you know.

Carl

0 Carl Blake over 13 years ago in reply to Carl Blake

Expert 1160 points

Hardik,

I've changed the TVP7002 driver to output a correct DE signal at all times (even during vertical blanking). This required making several changes to the file since some settings were not correct for the VBLK_F_1_START and VBLK_F_1_DURATION registers. I also discovered that the TVP7002's datasheet is incorrect as to the correct setting for AVID_START_PIXEL_MSBS bit 5. That bit has to be set to 1 if you want the AVID signal active during VBLK not 0 as the datasheet states. At any rate after I made these changes I confirmed that the TVP7002 was outputting a correct signal for hsync, vsync, and de (they were all active high) using an oscilloscope. The de signal was active at all times even during vertical blanking. I was able to trace all of the signals (except vsync) up to the resisters just before entering the 8168. Vsync was difficult to examine since its resistor is on the bottom of the board. I then ran the saLoopBackFbdev example program, but it did exactly the same thing. It starts the capture and then hangs the board. I have to reset the board to recover.

Any ideas?

Carl

0 HardikShah over 13 years ago in reply to Carl Blake

TI__Mastermind 20245 points

Hi,

Yes I meant DE as ACTVID signal. Truly speaking i have no idea whats going wrong here. I will have to debug this and see. I may not have time to start this as of now. Can you please give me register dump of following registers once it hangs.Do a telnet and get register dump.

Address from 0x48105500 to 0x481055B4. I will try to decode something from these registers. TVP7002 driver could also be wrong as i dont think its tested for RGB discrete sync.

Regards,

Hardik Shah

0 Carl Blake over 13 years ago in reply to HardikShah

Expert 1160 points

Hardik,

OK. Well I'm glad I made the correct changes to get the DE signal working. Unfortunately, I can't get a register dump. When I run saLoopBackFbdev the entire board hangs. You can't telnet in to the unit. I also tried running it in the background, but that didn't work either. Everything works until the capture starts. Once that starts the board is frozen.

By the way, what program could I use to get those registers dumped. Typically in a linux environment programs run in a virtual memory environment handled by the MMU. Is there a device, proc, or sys that I should access? Or do I access the registers through /dev/mem? I suppose I could use dd and /dev/mem. My initial attempts keep complaining about a bad address. I tried "dd if=/dev/mem bs=256 skip=4722773 count=1".

Carl

0 HardikShah over 13 years ago in reply to Carl Blake

TI__Mastermind 20245 points

Hi,

We have developed inhouse utility to read registers directly. You can use that for reading/writing registers. Please rename attached file to devmem_test.o. And enter ./devmem_test.o It will show you the usage.

Fullscreen 3157.devmem_test.txt Download

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0 Carl Blake over 13 years ago in reply to HardikShah

Expert 1160 points

Thanks.

However, remember that I am unable to dump the registers after I run saLoopBackFbdev since the system hangs. I have to do a reset of the board for it to start responding again. Telnet doesn't work and the uart console doesn't work.

Carl

0 Carl Blake over 13 years ago in reply to HardikShah

Expert 1160 points

Has there been any progress on solving this problem? I haven't heard anything for about 2 weeks now. It's absolutely essential that we be able to capture RGB888 video data. If the 8168 can't do this then we can't use the part since much of the input video data will be from computer sources. Have you been able to determine why the entire EVM hangs when attempting to process RGB data? I'm assuming that either there's either something wrong with the linux video input driver or the 8168's HDVPSS firmware has a problem with receiving RGB888 data and needs to be fixed. I need this resolved since we're trying to develop a product which we're hoping to release in the next few months. If there's something I can do to help figure this out please let me know. Obviously, if there's something wrong with the HDVPSS firmware I would be of limited help with that since much of that is proprietary to TI.

Please let me know what progress you're making and what I can do. Remember that I can't dump registers when the board hangs since it's frozen solid. Should I try and use kgdb to debug the kernel? If so could you give me some pointers as to how to proceed since I've never done that before.

Carl

0 Brijesh Jadav over 13 years ago in reply to Carl Blake

TI__Guru**** 475765 points

Hi Carl,

Linux TVP7002 driver does not support RGB capture. You will need to modify this driver to add support for RGB discrete sync output.

Thanks,

Brijesh Jadav

0 Carl Blake over 13 years ago in reply to Brijesh Jadav

Expert 1160 points

As stated in the very first post on this thread I have made the changes to the TVP7002 driver to support RGB capture. I described everything that I did in the hopes that someone with more experience with that driver would be able to tell me if I did something wrong or left something out. Would you mind reading that post and letting me know if there's something else I need to do to get this working?

Thanks.

Carl

0 Jun_Zhang over 13 years ago in reply to Carl Blake

Expert 2425 points

Hi Carl,

Have you been successfully make the evm can capture 24bit?

I notice that in the mux81xx.h file inside of linux-kernel, there are following codes.

My understanding that if you want to capture RGB wiht 24bits, you need define other vin0 pins. Here they only use 16bits.

#define TI816X_CONTROL_PADCONF_VIN0_D0_OFFSET           0x0950
#define TI816X_CONTROL_PADCONF_VIN0_D1_OFFSET           0x0954
#define TI816X_CONTROL_PADCONF_VIN0_D2_OFFSET           0x0958
#define TI816X_CONTROL_PADCONF_VIN0_D3_OFFSET           0x095C
#define TI816X_CONTROL_PADCONF_VIN0_D4_OFFSET           0x0960
#define TI816X_CONTROL_PADCONF_VIN0_D5_OFFSET           0x0964
#define TI816X_CONTROL_PADCONF_VIN0_D6_OFFSET           0x0968
#define TI816X_CONTROL_PADCONF_VIN0_D7_OFFSET           0x096C
#define TI816X_CONTROL_PADCONF_VIN0_D8_OFFSET           0x0970
#define TI816X_CONTROL_PADCONF_VIN0_D9_OFFSET           0x0974
#define TI816X_CONTROL_PADCONF_VIN0_D10_OFFSET           0x0978
#define TI816X_CONTROL_PADCONF_VIN0_D11_OFFSET           0x097C
#define TI816X_CONTROL_PADCONF_VIN0_D12_OFFSET           0x0980
#define TI816X_CONTROL_PADCONF_VIN0_D13_OFFSET           0x0984
#define TI816X_CONTROL_PADCONF_VIN0_D14_OFFSET           0x0988
#define TI816X_CONTROL_PADCONF_VIN0_D15_OFFSET           0x098C

Please let me know your feedback. I am also interested in capturing with 24 bits.

Thanks,

Jun

0 Carl Blake over 13 years ago in reply to Jun_Zhang

Expert 1160 points

Jun,

I hadn't noticed that before. However, on further investigation it looks like devices.c initializes vin0_d16 through vin0_d23 in ti81xx_video_mux for the 816x, so I don't think I need to define the other vin0 pins. I could be wrong about this. Even if I do need to initialize those pins that still doesn't explain why the entire EVM hangs when the saLoopBackFbdev program is run. I would have thought that the effect would be scrambled video not a hung processor.

I'm still working on this problem. So far I haven't gotten much help from TI yet. They helped by telling me I needed to change the TVP7002 driver, but they haven't explained why the changes I made cause a hung system and what I can do to get it working.

Carl

0 Carl Blake over 13 years ago in reply to Carl Blake

Expert 1160 points

I've been reading through the linux v4l2 drivers trying to determine why 24 bit RGB doesn't work and I noticed that ti81xxvid_main.c does not support 24 bit RGB. It specifically excludes it. I'm wondering if this is the source of the problem. The system does not hang until I turn video streaming on so this would make sense. I was wondering why support for 24 bit RGB was not included in ti81xxvid_main.c. Was it just forgotten or is there some specific reason why it should not be added? I was thinking I would make an attempt to add 24 bit RGB support into that driver if there's no problem with doing that. I also noticed that the maximum buffer size is 4 MBytes. Is there a problem with increasing that in the driver so that I can support 1920x1080 24 bit RGB? It would mean increasing the maximum buffer size to 6,220,800. Is there a problem with doing this? Would it cause a problem somewhere else in the system?

Please let me know about these issues as soon as possible.

Carl

0 Carl Blake over 13 years ago in reply to Carl Blake

Expert 1160 points

OK. New information. I made the changes I discussed above to ti81xxvid_main.c in which I added support for 24 bit RGB to the driver. I was unable to increase the size of the buffers since linux was unable to register the video driver when I did that, so I'm just working with lower resolution video at this point (1280x720). I'm assuming that I need to increase the size of the vram setting when I start linux to get that working. I'm not worrying about that yet.

The result is that the system no longer crashes and burns when I run saLoopBackFbdev. It doesn't work, but it doesn't crash. I can now telnet in and read the registers Hardik asked about. It looks like its not able to see any vsyncs, because it starts the loop after turning streaming on, but then hangs on the ioctl vsync call.

The registers for 0x48105500 are:

48105500: 01 00 00 00 10 a5 00 80 00 00 00 00 00 00 00 00
48105510: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
48105520: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
48105530: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
48105540: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
48105550: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
48105560: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
48105570: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
48105580: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
48105590: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
481055a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
481055b0: 00 00 00 00

Carl

0 Carl Blake over 13 years ago in reply to Carl Blake

Expert 1160 points

Further investigation has revealed that saLoopBackFbdev is NOT stopping while waiting for a vsync. It's stopping at the VIDIOC_DQBUF ioctl. Any ideas why?

Carl

0 HardikShah over 13 years ago in reply to Carl Blake

TI__Mastermind 20245 points

Hi,

VIDIOC_DQBUF is a blocking call from application. It means that you are not received any data from capture driver. In that case DQBUF will infinitely block till you get data. So problem is with catpure driver not the display or fbdev driver.

Regards,

Hardik shah

0 HardikShah over 13 years ago in reply to HardikShah

TI__Mastermind 20245 points

Forgot to add,

V4L2 doesn't support 24bit RGB it only support YUV422. So you have to use graphics driver only for displaying captured RGB data.

Regards,

Hardik Shah

0 Carl Blake over 13 years ago in reply to HardikShah

Expert 1160 points

Hardik,

OK, this is a very important point. For our application we HAVE to capture and display video at 24 bit RGB. Much of our video will be from computers not from blue ray players or cameras, so it's very important that we can do 24 bit RGB. If V4L2 doesn't support 24 bit RGB then we can't use it. Can you tell me how we can make this work? What method should we use? I thought the example in saLoopBackFbdev showed a method of capturing using the graphics driver which could also be used for 24 bit RGB. Is this not true? HELP!!

Carl

0 HardikShah over 13 years ago in reply to Carl Blake

TI__Mastermind 20245 points

Hi,

You are right you can use saLoopBackFbdev to display the captured image on graphics plane. Alternatively you can also convert it to YUV using the VIP and display it using V4L2.

Regards,

Hardik Shah

0 Carl Blake over 13 years ago in reply to HardikShah

Expert 1160 points

That's good. But you still haven't answered my question about being able to capture RGB 24 bit. I can't use YUV422, I need to be able to capture RGB 24 bit or YUV444. Do you have an answer to this? Is there a way to do it? I can't tell if you're working on finding an answer or not. Please give me some feedback. I've been pouring over the linux driver code trying to figure out why it won't work without success for a few weeks now. I'm starting to get pretty discouraged.

Carl

0 HardikShah over 13 years ago in reply to Carl Blake

TI__Mastermind 20245 points

Hi,

RGB24 bit capture is possible with Vin0 port. Its not possible with Vin1 port on DM816x since only 16 data pins are available. We have successfully captured RGB24 bit with TVP7002 driver from Media controller.

Regards,

Hardik shah

0 Carl Blake over 13 years ago in reply to HardikShah

Expert 1160 points

Hardik,

It's great that you've successfully captured RGB24 bit with the TVP7002 driver from the Media controller. Would you mind sharing how you did it? As far as I can tell I've made all the changes necessary to arch/arm/mach-omap2/ti81xx_fb.c, drivers/media/video/tvp7002.c, drivers/media/video/ti81xx/ti81xxvid_main.c, and drivers/media/video/ti81xx/ti81xxvin_main.c toget the TVP7002 to output discrete hsync and vsync and configure everything for RGB24. I'm using Vin0 not Vin1. I've tried to tell the system that it should be receiving discrete hsync and vsync and RGB 24. I'm using the example code from saLoopBackFbdev.c. But it crashes the system. I have to reset or power cycle the board to bring it back. If you could tell me the steps you took to change from YUV422 to RGB24 that would be great.

Carl

0 HardikShah over 13 years ago in reply to Carl Blake

TI__Mastermind 20245 points

Hi,

Thats on my todo list. I will try to share register settings for both TVP and VIP for discrete sync capture with RGB.

Regards,

Hardik shah

0 BenM over 13 years ago in reply to HardikShah

Expert 2220 points

Hardik,

I'd like to throw my hat in the ring and say that I am also need to know how to do this. Please share!

Thanks,

Ben

0 HardikShah over 13 years ago in reply to BenM

TI__Mastermind 20245 points

Hi,

I am able to capture RGB from TVP7002 and dump RGB to memory using our Media controller binary. Here are register settings for TVP7002 and VIP for capturing SXGA@60 FPS. Please let me know in case you are not able to progress. Best is to do following steps to make RGB capture work.

1. Configure V4L2 driver for RGB input

2. Configure TVP7002 for RGB input

3. Dont start TVP7002, but do streamon. This will ensure all VIP registers are configured but no data is received.

4. Dump 256 VIP registers from address 0x48105500

5. Compare with registers provided here. Send the register dump if its different.

6. Now start TVP7002 but dont start VIP. Dump TVP7002 registers and compare with TVP7002 registers attached with this thread. If they are not same find the reason and fix it.

Fullscreen 2260.tvp7002_sxga.log Download

[CortexM3_ISS_0]  I2C-1> rd 5d 0 FF
[CortexM3_ISS_0]  I2C: Reading 0xff registers starting from REG 0x00 of device 0x5d ... !!!
[CortexM3_ISS_0]  I2C: 0x00 = 0x02
[CortexM3_ISS_0]  I2C: 0x01 = 0x69
[CortexM3_ISS_0]  I2C: 0x02 = 0x80
[CortexM3_ISS_0]  I2C: 0x03 = 0xa0
[CortexM3_ISS_0]  I2C: 0x04 = 0x80
[CortexM3_ISS_0]  I2C: 0x05 = 0x06
[CortexM3_ISS_0]  I2C: 0x06 = 0x10
[CortexM3_ISS_0]  I2C: 0x07 = 0x20
[CortexM3_ISS_0]  I2C: 0x08 = 0x00
[CortexM3_ISS_0]  I2C: 0x09 = 0x00
[CortexM3_ISS_0]  I2C: 0x0a = 0x00
[CortexM3_ISS_0]  I2C: 0x0b = 0x80
[CortexM3_ISS_0]  I2C: 0x0c = 0x80
[CortexM3_ISS_0]  I2C: 0x0d = 0x80
[CortexM3_ISS_0]  I2C: 0x0e = 0x52
[CortexM3_ISS_0]  I2C: 0x0f = 0x2e
[CortexM3_ISS_0]  I2C: 0x10 = 0x5d
[CortexM3_ISS_0]  I2C: 0x11 = 0x20
[CortexM3_ISS_0]  I2C: 0x12 = 0x01
[CortexM3_ISS_0]  I2C: 0x13 = 0x00
[CortexM3_ISS_0]  I2C: 0x14 = 0xb5
[CortexM3_ISS_0]  I2C: 0x15 = 0x04
[CortexM3_ISS_0]  I2C: 0x16 = 0x11
[CortexM3_ISS_0]  I2C: 0x17 = 0x12
[CortexM3_ISS_0]  I2C: 0x18 = 0x00
[CortexM3_ISS_0]  I2C: 0x19 = 0xaa
[CortexM3_ISS_0]  I2C: 0x1a = 0x6a
[CortexM3_ISS_0]  I2C: 0x1b = 0x77
[CortexM3_ISS_0]  I2C: 0x1c = 0x07
[CortexM3_ISS_0]  I2C: 0x1d = 0x00
[CortexM3_ISS_0]  I2C: 0x1e = 0x10
[CortexM3_ISS_0]  I2C: 0x1f = 0x10
[CortexM3_ISS_0]  I2C: 0x20 = 0x10
[CortexM3_ISS_0]  I2C: 0x21 = 0x08
[CortexM3_ISS_0]  I2C: 0x22 = 0x00
[CortexM3_ISS_0]  I2C: 0x23 = 0x21
[CortexM3_ISS_0]  I2C: 0x24 = 0x63
[CortexM3_ISS_0]  I2C: 0x25 = 0x0c
[CortexM3_ISS_0]  I2C: 0x26 = 0x80
[CortexM3_ISS_0]  I2C: 0x27 = 0x08
[CortexM3_ISS_0]  I2C: 0x28 = 0x53
[CortexM3_ISS_0]  I2C: 0x29 = 0x08
[CortexM3_ISS_0]  I2C: 0x2a = 0x07
[CortexM3_ISS_0]  I2C: 0x2b = 0x00
[CortexM3_ISS_0]  I2C: 0x2c = 0x50
[CortexM3_ISS_0]  I2C: 0x2d = 0x00
[CortexM3_ISS_0]  I2C: 0x2e = 0x80
[CortexM3_ISS_0]  I2C: 0x2f = 0x8c
[CortexM3_ISS_0]  I2C: 0x30 = 0x04
[CortexM3_ISS_0]  I2C: 0x31 = 0x18
[CortexM3_ISS_0]  I2C: 0x32 = 0x18
[CortexM3_ISS_0]  I2C: 0x33 = 0x60
[CortexM3_ISS_0]  I2C: 0x34 = 0x03
[CortexM3_ISS_0]  I2C: 0x35 = 0x10
[CortexM3_ISS_0]  I2C: 0x36 = 0x00
[CortexM3_ISS_0]  I2C: 0x37 = 0x2a
[CortexM3_ISS_0]  I2C: 0x38 = 0x24
[CortexM3_ISS_0]  I2C: 0x39 = 0xa6
[CortexM3_ISS_0]  I2C: 0x3a = 0x01
[CortexM3_ISS_0]  I2C: 0x3b = 0x1c
[CortexM3_ISS_0]  I2C: 0x3c = 0x03
[CortexM3_ISS_0]  I2C: 0x3d = 0x03
[CortexM3_ISS_0]  I2C: 0x3e = 0x04
[CortexM3_ISS_0]  I2C: 0x3f = 0x00
[CortexM3_ISS_0]  I2C: 0x40 = 0x80
[CortexM3_ISS_0]  I2C: 0x41 = 0x01
[CortexM3_ISS_0]  I2C: 0x42 = 0x86
[CortexM3_ISS_0]  I2C: 0x43 = 0x06
[CortexM3_ISS_0]  I2C: 0x44 = 0x00
[CortexM3_ISS_0]  I2C: 0x45 = 0x00
[CortexM3_ISS_0]  I2C: 0x46 = 0x01
[CortexM3_ISS_0]  I2C: 0x47 = 0x01
[CortexM3_ISS_0]  I2C: 0x48 = 0x00
[CortexM3_ISS_0]  I2C: 0x49 = 0x00
[CortexM3_ISS_0]  I2C: 0x4a = 0xe3
[CortexM3_ISS_0]  I2C: 0x4b = 0x16
[CortexM3_ISS_0]  I2C: 0x4c = 0x4f
[CortexM3_ISS_0]  I2C: 0x4d = 0x02
[CortexM3_ISS_0]  I2C: 0x4e = 0xce
[CortexM3_ISS_0]  I2C: 0x4f = 0x06
[CortexM3_ISS_0]  I2C: 0x50 = 0xab
[CortexM3_ISS_0]  I2C: 0x51 = 0xf3
[CortexM3_ISS_0]  I2C: 0x52 = 0x00
[CortexM3_ISS_0]  I2C: 0x53 = 0x10
[CortexM3_ISS_0]  I2C: 0x54 = 0x55
[CortexM3_ISS_0]  I2C: 0x55 = 0xfc
[CortexM3_ISS_0]  I2C: 0x56 = 0x78
[CortexM3_ISS_0]  I2C: 0x57 = 0xf1
[CortexM3_ISS_0]  I2C: 0x58 = 0x88
[CortexM3_ISS_0]  I2C: 0x59 = 0xfe
[CortexM3_ISS_0]  I2C: 0x5a = 0x00
[CortexM3_ISS_0]  I2C: 0x5b = 0x10
[CortexM3_ISS_0]  I2C: 0x5c = 0x00
[CortexM3_ISS_0]  I2C: 0x5d = 0x00
[CortexM3_ISS_0]  I2C: 0x5e = 0x00
[CortexM3_ISS_0]  I2C: 0x5f = 0x00
[CortexM3_ISS_0]  I2C: 0x60 = 0x00
[CortexM3_ISS_0]  I2C: 0x61 = 0x00
[CortexM3_ISS_0]  I2C: 0x62 = 0x00
[CortexM3_ISS_0]  I2C: 0x63 = 0x00
[CortexM3_ISS_0]  I2C: 0x64 = 0x00
[CortexM3_ISS_0]  I2C: 0x65 = 0x00
[CortexM3_ISS_0]  I2C: 0x66 = 0x00
[CortexM3_ISS_0]  I2C: 0x67 = 0x00
[CortexM3_ISS_0]  I2C: 0x68 = 0x00
[CortexM3_ISS_0]  I2C: 0x69 = 0x00
[CortexM3_ISS_0]  I2C: 0x6a = 0x00
[CortexM3_ISS_0]  I2C: 0x6b = 0x00
[CortexM3_ISS_0]  I2C: 0x6c = 0x00
[CortexM3_ISS_0]  I2C: 0x6d = 0x00
[CortexM3_ISS_0]  I2C: 0x6e = 0x00
[CortexM3_ISS_0]  I2C: 0x6f = 0x00
[CortexM3_ISS_0]  I2C: 0x70 = 0x00
[CortexM3_ISS_0]  I2C: 0x71 = 0x00
[CortexM3_ISS_0]  I2C: 0x72 = 0x00
[CortexM3_ISS_0]  I2C: 0x73 = 0x00
[CortexM3_ISS_0]  I2C: 0x74 = 0x00
[CortexM3_ISS_0]  I2C: 0x75 = 0x00
[CortexM3_ISS_0]  I2C: 0x76 = 0x00
[CortexM3_ISS_0]  I2C: 0x77 = 0x00
[CortexM3_ISS_0]  I2C: 0x78 = 0x00
[CortexM3_ISS_0]  I2C: 0x79 = 0x00
[CortexM3_ISS_0]  I2C: 0x7a = 0x00
[CortexM3_ISS_0]  I2C: 0x7b = 0x00
[CortexM3_ISS_0]  I2C: 0x7c = 0x00
[CortexM3_ISS_0]  I2C: 0x7d = 0x00
[CortexM3_ISS_0]  I2C: 0x7e = 0x00
[CortexM3_ISS_0]  I2C: 0x7f = 0x00
[CortexM3_ISS_0]  I2C: 0x80 = 0x00
[CortexM3_ISS_0]  I2C: 0x81 = 0x00
[CortexM3_ISS_0]  I2C: 0x82 = 0x00
[CortexM3_ISS_0]  I2C: 0x83 = 0x00
[CortexM3_ISS_0]  I2C: 0x84 = 0x00
[CortexM3_ISS_0]  I2C: 0x85 = 0x00
[CortexM3_ISS_0]  I2C: 0x86 = 0x00
[CortexM3_ISS_0]  I2C: 0x87 = 0x00
[CortexM3_ISS_0]  I2C: 0x88 = 0x00
[CortexM3_ISS_0]  I2C: 0x89 = 0x00
[CortexM3_ISS_0]  I2C: 0x8a = 0x00
[CortexM3_ISS_0]  I2C: 0x8b = 0x00
[CortexM3_ISS_0]  I2C: 0x8c = 0x00
[CortexM3_ISS_0]  I2C: 0x8d = 0x00
[CortexM3_ISS_0]  I2C: 0x8e = 0x00
[CortexM3_ISS_0]  I2C: 0x8f = 0x00
[CortexM3_ISS_0]  I2C: 0x90 = 0x00
[CortexM3_ISS_0]  I2C: 0x91 = 0x00
[CortexM3_ISS_0]  I2C: 0x92 = 0x00
[CortexM3_ISS_0]  I2C: 0x93 = 0x00
[CortexM3_ISS_0]  I2C: 0x94 = 0x00
[CortexM3_ISS_0]  I2C: 0x95 = 0x00
[CortexM3_ISS_0]  I2C: 0x96 = 0x00
[CortexM3_ISS_0]  I2C: 0x97 = 0x00
[CortexM3_ISS_0]  I2C: 0x98 = 0x00
[CortexM3_ISS_0]  I2C: 0x99 = 0x00
[CortexM3_ISS_0]  I2C: 0x9a = 0x00
[CortexM3_ISS_0]  I2C: 0x9b = 0x00
[CortexM3_ISS_0]  I2C: 0x9c = 0x00
[CortexM3_ISS_0]  I2C: 0x9d = 0x00
[CortexM3_ISS_0]  I2C: 0x9e = 0x00
[CortexM3_ISS_0]  I2C: 0x9f = 0x00
[CortexM3_ISS_0]  I2C: 0xa0 = 0x00
[CortexM3_ISS_0]  I2C: 0xa1 = 0x00
[CortexM3_ISS_0]  I2C: 0xa2 = 0x00
[CortexM3_ISS_0]  I2C: 0xa3 = 0x00
[CortexM3_ISS_0]  I2C: 0xa4 = 0x00
[CortexM3_ISS_0]  I2C: 0xa5 = 0x00
[CortexM3_ISS_0]  I2C: 0xa6 = 0x00
[CortexM3_ISS_0]  I2C: 0xa7 = 0x00
[CortexM3_ISS_0]  I2C: 0xa8 = 0x00
[CortexM3_ISS_0]  I2C: 0xa9 = 0x00
[CortexM3_ISS_0]  I2C: 0xaa = 0x00
[CortexM3_ISS_0]  I2C: 0xab = 0x00
[CortexM3_ISS_0]  I2C: 0xac = 0x00
[CortexM3_ISS_0]  I2C: 0xad = 0x00
[CortexM3_ISS_0]  I2C: 0xae = 0x00
[CortexM3_ISS_0]  I2C: 0xaf = 0x00
[CortexM3_ISS_0]  I2C: 0xb0 = 0x00
[CortexM3_ISS_0]  I2C: 0xb1 = 0x00
[CortexM3_ISS_0]  I2C: 0xb2 = 0x00
[CortexM3_ISS_0]  I2C: 0xb3 = 0x00
[CortexM3_ISS_0]  I2C: 0xb4 = 0x00
[CortexM3_ISS_0]  I2C: 0xb5 = 0x00
[CortexM3_ISS_0]  I2C: 0xb6 = 0x00
[CortexM3_ISS_0]  I2C: 0xb7 = 0x00
[CortexM3_ISS_0]  I2C: 0xb8 = 0x00
[CortexM3_ISS_0]  I2C: 0xb9 = 0x00
[CortexM3_ISS_0]  I2C: 0xba = 0x00
[CortexM3_ISS_0]  I2C: 0xbb = 0x00
[CortexM3_ISS_0]  I2C: 0xbc = 0x00
[CortexM3_ISS_0]  I2C: 0xbd = 0x00
[CortexM3_ISS_0]  I2C: 0xbe = 0x00
[CortexM3_ISS_0]  I2C: 0xbf = 0x00
[CortexM3_ISS_0]  I2C: 0xc0 = 0x00
[CortexM3_ISS_0]  I2C: 0xc1 = 0x00
[CortexM3_ISS_0]  I2C: 0xc2 = 0x00
[CortexM3_ISS_0]  I2C: 0xc3 = 0x00
[CortexM3_ISS_0]  I2C: 0xc4 = 0x00
[CortexM3_ISS_0]  I2C: 0xc5 = 0x00
[CortexM3_ISS_0]  I2C: 0xc6 = 0x00
[CortexM3_ISS_0]  I2C: 0xc7 = 0x00
[CortexM3_ISS_0]  I2C: 0xc8 = 0x00
[CortexM3_ISS_0]  I2C: 0xc9 = 0x00
[CortexM3_ISS_0]  I2C: 0xca = 0x00
[CortexM3_ISS_0]  I2C: 0xcb = 0x00
[CortexM3_ISS_0]  I2C: 0xcc = 0x00
[CortexM3_ISS_0]  I2C: 0xcd = 0x00
[CortexM3_ISS_0]  I2C: 0xce = 0x00
[CortexM3_ISS_0]  I2C: 0xcf = 0x00
[CortexM3_ISS_0]  I2C: 0xd0 = 0x00
[CortexM3_ISS_0]  I2C: 0xd1 = 0x00
[CortexM3_ISS_0]  I2C: 0xd2 = 0x00
[CortexM3_ISS_0]  I2C: 0xd3 = 0x00
[CortexM3_ISS_0]  I2C: 0xd4 = 0x00
[CortexM3_ISS_0]  I2C: 0xd5 = 0x00
[CortexM3_ISS_0]  I2C: 0xd6 = 0x00
[CortexM3_ISS_0]  I2C: 0xd7 = 0x00
[CortexM3_ISS_0]  I2C: 0xd8 = 0x00
[CortexM3_ISS_0]  I2C: 0xd9 = 0x00
[CortexM3_ISS_0]  I2C: 0xda = 0x00
[CortexM3_ISS_0]  I2C: 0xdb = 0x00
[CortexM3_ISS_0]  I2C: 0xdc = 0x00
[CortexM3_ISS_0]  I2C: 0xdd = 0x00
[CortexM3_ISS_0]  I2C: 0xde = 0x00
[CortexM3_ISS_0]  I2C: 0xdf = 0x00
[CortexM3_ISS_0]  I2C: 0xe0 = 0x00
[CortexM3_ISS_0]  I2C: 0xe1 = 0x00
[CortexM3_ISS_0]  I2C: 0xe2 = 0x00
[CortexM3_ISS_0]  I2C: 0xe3 = 0x00
[CortexM3_ISS_0]  I2C: 0xe4 = 0x00
[CortexM3_ISS_0]  I2C: 0xe5 = 0x00
[CortexM3_ISS_0]  I2C: 0xe6 = 0x00
[CortexM3_ISS_0]  I2C: 0xe7 = 0x00
[CortexM3_ISS_0]  I2C: 0xe8 = 0x00
[CortexM3_ISS_0]  I2C: 0xe9 = 0x00
[CortexM3_ISS_0]  I2C: 0xea = 0x00
[CortexM3_ISS_0]  I2C: 0xeb = 0x00
[CortexM3_ISS_0]  I2C: 0xec = 0x00
[CortexM3_ISS_0]  I2C: 0xed = 0x00
[CortexM3_ISS_0]  I2C: 0xee = 0x00
[CortexM3_ISS_0]  I2C: 0xef = 0x00
[CortexM3_ISS_0]  I2C: 0xf0 = 0x00
[CortexM3_ISS_0]  I2C: 0xf1 = 0x00
[CortexM3_ISS_0]  I2C: 0xf2 = 0x00
[CortexM3_ISS_0]  I2C: 0xf3 = 0x00
[CortexM3_ISS_0]  I2C: 0xf4 = 0x00
[CortexM3_ISS_0]  I2C: 0xf5 = 0x00
[CortexM3_ISS_0]  I2C: 0xf6 = 0x00
[CortexM3_ISS_0]  I2C: 0xf7 = 0x00
[CortexM3_ISS_0]  I2C: 0xf8 = 0x00
[CortexM3_ISS_0]  I2C: 0xf9 = 0x00
[CortexM3_ISS_0]  I2C: 0xfa = 0x00
[CortexM3_ISS_0]  I2C: 0xfb = 0x00
[CortexM3_ISS_0]  I2C: 0xfc = 0x00
[CortexM3_ISS_0]  I2C: 0xfd = 0x00
[CortexM3_ISS_0]  I2C: 0xfe = 0x00
[CortexM3_ISS_0]  I2C: Read Done !!!
[CortexM3_ISS_0]  I2C: Time Elapsed in Read = 38 msec 
[CortexM3_ISS_0]  I2C-1>

Fullscreen 2605.vip_regs.log Download

1651 1 48105500 0 100
0x00000000
0x0000A10A
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000400
0xFFFFFFFC
0xFFFFFFFC
0xFFFFFFFF
0xFFFFFFFF
0x04FF0427
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x0000A10A
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000400
0xFFFFFFFC
0xFFFFFFFC
0xFFFFFFFF
0xFFFFFFFF
0x04FF0427
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
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0x00000000
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0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00004000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0xFC000000
0x0C840800
0x00100010
0x00040190
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00004000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0xFC000000
0x0C840800
0x00100010
0x00040190
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000

Regards,

Hardik Shah

0 Carl Blake over 13 years ago in reply to HardikShah

Expert 1160 points

Thank you for the information.

I have a few questions:

It's unclear to me how you don't start TVP7002, but do streamon. I'm assuming these steps need to be done in a program since doing streamon is typically an ioctl command. How do you not start TVP7002? You have to load the TVP7002 module if you want to do a streamon (because you have to open /dev/video0 before you can send the ioctl streamon command). What do you mean by this? After you've done the streamon how do you start TVP7002?

I have similar questions about not starting and starting the VIP. What steps do you take to start it and what steps do you take to not start it?

I know these may seem like very basic questions, but I've never seen a description of stopping and starting these systems in this manner.

Carl

0 HardikShah over 13 years ago in reply to Carl Blake

TI__Mastermind 20245 points

Yes,

This is required for debugging. Normally all these steps which i asked for is not required. You can do following things

For doing streamon but not starting TVP7002 you will have to comment following line in code. This will ensure that VIP is started for receiving but wont receive any data since TVP7002 is not started. When you do streamon below line is called to start TVP. Commenting out below line will ensure that everything is done as if streamon is started by TVP7002 wont start. Take register dump of VIP registers after doing this 0x48105500 first 256 registers.

ret = v4l2_subdev_call(ti81xxvin_obj.sd[inst->curr_sd_index], video, s_stream, 1);

For doing streamon but not starting VIP you have to comment follwing line. This will ensure that TVP7002 is started but VIP is not started so although you send data through TVP7002 VIP wont receive. Make sure that you un-comment the above line commented earlier. Now take dump of TVP7002 registers. It needs to be done through I2C. You can put hack in TVP7002 driver to print the registers before its getting programmed.

ret = ti81xxvin_vps_start(inst);

Once you get both register dump you can compare with the one I sent and figure it out whether its a problem with VIP settings or TVP7002 settings.

Regards,

Hardik Shah

0 Carl Blake over 13 years ago in reply to HardikShah

Expert 1160 points

Hardik,

I've attached an i2c register dump of the TVP7002. This is the register settings with ti81xxvin_vps_start commented out in drivers/media/video/ti81xx/ti81xxvin_main.c and with saLoopBackFbdev running.

When I attempted to run saLoopBackFbdev with ti81xxvin_vps_start uncommented and v4l2_subdev_call which turns streaming on commented out the system hung again, so I was unable to get a register dump from 0x48105500.

It would appear that the system hangs when ti81xxvin_vps_start is called. It looks to me like something's wrong with the VIP setup. I believe I setup everything I needed to to get the VIP to support RGB 24 bit external hsync and vsync. Most of those changes were done in ti81xxvid_main.c and involved adding support for the V4L2_PIX_FMT_RGB24 pixel format. Is there something else you can think of that I need to do to the VIP drivers to get this working? Would you be able to send me the files you had to change to support 24 bit RGB?

Carl

TVP7002 register dump - setup for RGB 24bit

02 67 20 a0 16 32 20 60 00 00 00 80 80 80 24 2e
5d 47 00 00 6f 04 01 10 01 00 67 77 07 00 10 10
10 08 00 3b 49 43 80 08 53 08 07 00 50 00 80 00
04 5a 18 60 03 10 00 0d 22 d0 00 0f 06 03 04 01
47 21 4b 06 05 05 1e 1e 00 00 e3 16 4f 02 ce 06
ab f3 00 10 55 fc 78 f1 88 fe 00 10 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0 HardikShah over 13 years ago in reply to Carl Blake

TI__Mastermind 20245 points

Hi,

Can you please analyze the key differences between the dump I took and dump you have. Please make sure that yo have taken TVP7002 dump with SXGA resolution and RGB out from TVP7002. Right now dont worry for VIP hang, you will be able to find the TVP7002 datasheet at http://www.ti.com/product/tvp7002. I have done RGB capture using our M3 firmware and not the Linux driver so I have not modified ti81xx_vps.c as of now. We will look VIP hang once we are sure that TVP7002 setting are done properly and TVP7002 is sending required data in proper format.

Regards,

Hardik Shah

0 XUEBIN WEN1 over 12 years ago in reply to Carl Blake

Intellectual 395 points

HI could you share discrete sync with me please. we has same problem,my email is my_dream0011@163.com

thanks

Processors

Processors forum

Changing TVP7002 interface from YUV422 to RGB