My customer is looking to choose flash memory for the AM3892 processor. He wants to be sure that he can use the ROM bootloader capability in that part. He plans to use the MT29F8G08ABABAWPIT:B part, which is a 1 GByte (1 Gbit x 8) NAND TSOP and is seeing conflicting informaiton on just what is compatible with the RBL.
Here are his questions:
1. I’ve seen TI recommend part numbers for this board that happen to be 2 GByte parts, yet the GPMC documentation in the SPRUGX7 document says that it has a maximum chip capacity of 256 MB. Would I be correct in assuming that larger chip sizes are supported, but that only 256 MB is accessible?
2. I’ve seen a part recommended that used a very large page size, 4096 bytes + 224 spare bytes. When I look at the SPRUGX7 document, it mentions that 4096 bytes + 128/218 spare bytes is supported. Is there an issue with using a part with the 224 spare bytes? I would assume not since that would just be extra ECC capacity, but I thought that I’d ask.
3. It uses the term “CE don’t care devices only.” I’m not sure what the document means by that. I’ve seen it use both CE and CS (chip enable and chip select) and it doesn’t seem to use them interchangeably. I’m going to need to use some sort of chip select since I plan to have multiple devices hooked to the GPMC, and I’m going to need some way of triggering them independently. Does “CE don’t care” mean that the device has to respond to any request, independent of chip select? It says that the device must be hooked to CS0, which implies to me that they mean something else when they says “CE don’t care devices only.”
4. The device mentions a 55 MHz GPMC clock. Elsewhere in the documentation it says that the GPMC is fed by SYSCLK6, which is clocked at 125 MHz, and has divider options of 1, 2, 4, and 8. You can’t get 55 MHz from any of those options, so I must be getting confused somewhere.
I am trying to stay with this part because Micron’s selection of TSOPs in an extended temperature range is getting fairly thin. Hopefully TI can help me make sure that I can use the RBL capability with this particular NAND part.
>>>>document says that it has a maximum chip capacity of 256 MB
The limit of GPMC supporting maximum of 256MB is only for NOR devices, For Nand devices , this limit does not apply
Reason is:: NOR devices work on a Random access like requests. ::::. Address1,Dataset1 ; Address2,Dataset2 ....
Where as Nand devices work on block transfer basis :::: <PageWriteOpensequence_indicating startaddress_and_numberofBytes> , Data1,Data2,Data3,........DataLast.
>>>>page size, 4096 bytes + 224 spare bytes. Vs 4096 bytes + 128/218 spare bytes
The S/W may need to be modified, if the plan is to use sequences trying to write multiple pages.
>>>>It uses the term “CE don’t care devices only.”
Not sure which document and which part is being referred.
The GPMC functionality normally enables the corresponding CS (Chip select, connected normally to CE/Chip enable)
before initiating any data transfer.
>>>>The device mentions a 55 MHz GPMC clock. Vs SYSCLK6, which is clocked at 125 MHz
Question not clear.
Nand devices act on asynchronous mode of transfer, in which no clock is given to memory from GPMC.
Best regards,
Chaitanya vahni
Front-end specialist, TI India
GPMC Design owner.