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TI Home » TI E2E Community » Support Forums » Digital Signal Processors (DSP) » DaVinci™ Video Processors » DM816x, C6A816x and AM389x Processors Forum » The glitch occurs on I2C0 SDA of DM8168
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The glitch occurs on I2C0 SDA of DM8168

The glitch occurs on I2C0 SDA of DM8168

This question is answered
OC
Posted by OC
on May 02 2012 20:29 PM
Intellectual870 points

Dear all,

I measure the I2C waveform on DM8168EVM(rev C). It occurs the glitch on I2C0 SDA. Please refer the below waveform. Can anyone provide me the solution to eliminate it?

Thanks in advance.

B.R.

OC

 

 

I2C DM8168EVM
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  • Steve Clynes
    Posted by Steve Clynes
    on May 03 2012 12:09 PM
    Verified Answer
    Verified by OC
    Mastermind22790 points

    This is not a glitch per se. It is simple the bus being released at the end of the cycle and is allowed as per the I2C spec as long as it does not occur whilst CLK is high.

    It is difficult to see from the capture, but this might simply be the ACK period, where it would be the responsibility of the slave device to hold data low for the ACK cycle. If there is no slave device responding to the message then it would also cause SDA to go high.

    BR,

    Steve

    Please mark this post as answered via the Verify Answer button below if you think it answers your question.  Thanks!

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  • OC
    Posted by OC
    on May 13 2012 09:56 AM
    Intellectual870 points

    Dear Steve,

    Thanks for your clarification on this concern. It's clear for me now.

    B.R.

    OC

    I2C DM8168EVM
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