dm8168 vip1 input

BTW:our software platform:ezsdk_dm816x-evm_5_04_00_11

Only you can tell how your pins should be from your schematic. It's worth being careful not to get confused as some of the video input pins can be assigned to more than one physical pin.

Starting system message bus: dbus.
Starting telnet daemon.
Starting syslogd/klogd: done
Starting thttpd.
Starting PVR
Starting Matrix GUI application.
i am in matrix-gui-e 22222!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Stopping Matrix GUI application.
Stopping PVR
ti81xx_vidout_probe ok!!!!!
insmod ti81xxvo done
insmod ti81xxvin done
tvp7002 2-0021: tvp7002 found @ 0x21 (OMAP I2C adapter)
tvp7002 2-0021: Rev. 04 detected.
tvp7002 2-0021: Write: retry ... 0
tvp7002 2-0021: Write: retry ... 1
tvp7002 2-0021: Write: retry ... 2
tvp7002 2-0021: Write: retry ... 3
tvp7002 2-0021: Write: retry ... 4
tvp7002 2-0021: TVP7002 write error -121 at reg:f
ti81xxvin ti81xxvin: registered sub device tvp7002
ti81xxvin ti81xxvin: TI81xx HDVPSS Capture driver initialized

 _____                    _____           _         _  
|  _  |___ ___ ___ ___   |  _  |___ ___  |_|___ ___| |_
|     |  _| .'| . | . |  |   __|  _| . | | | -_|  _|  _|
|__|__|_| |__,|_  |___|  |__|  |_| |___|_| |___|___|_| 
              |___|                    |___|          

Arago Project http://arago-project.org dm816x-evm ttyO2

Arago 2011.09 dm816x-evm ttyO2

dm816x-evm login:

==================================================

tvp7002 2-0021: tvp7002 found @ 0x21 (OMAP I2C adapter)      ==>0x21 ,infact,it's adv7441' i2c addr,adv7441 is for vip0 input.

but there is not instance 1,it's for vip1 input?why?

 =================================================

ti81xx_vpss.c:

static struct ti81xxvin_subdev_info hdvpss_capture_sdev_info[] = {
 {
  .name = TVP7002_INST0,
  .board_info = {
   /* TODO Find the correct address
    of the TVP7002 connected */
//   I2C_BOARD_INFO("tvp7002", 0x5d),
   I2C_BOARD_INFO("tvp7002", (0x42>>1)),  //haha.gao test 0x42 is adv7441 user map
   .platform_data = &tvp7002_pdata,
  },
  .vip_port_cfg = {
   .ctrlChanSel = VPS_VIP_CTRL_CHAN_SEL_15_8,
   .ancChSel8b = VPS_VIP_ANC_CH_SEL_DONT_CARE,
   .pixClkEdgePol = VPS_VIP_PIX_CLK_EDGE_POL_RISING,
   .invertFidPol = 0,
   .embConfig = {
    .errCorrEnable = 1,
    .srcNumPos = VPS_VIP_SRC_NUM_POS_DONT_CARE,
    .isMaxChan3Bits = 0,
   },
   .disConfig = {
    .fidSkewPostCnt = 0,
    .fidSkewPreCnt = 0,
    .lineCaptureStyle =
     VPS_VIP_LINE_CAPTURE_STYLE_DONT_CARE,
    .fidDetectMode =
     VPS_VIP_FID_DETECT_MODE_DONT_CARE,
    .actvidPol = VPS_VIP_POLARITY_DONT_CARE,
    .vsyncPol =  VPS_VIP_POLARITY_DONT_CARE,
    .hsyncPol = VPS_VIP_POLARITY_DONT_CARE,
   }
  },
  .video_capture_mode =
     VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_EMBEDDED_SYNC,
  .video_if_mode = VPS_CAPT_VIDEO_IF_MODE_16BIT,
  .input_data_format = FVID2_DF_YUV422P,
 },
 {
  .name = TVP7002_INST1,
  .board_info = {
   I2C_BOARD_INFO("tvp7002", 0x5c),
   .platform_data = &tvp7002_pdata,
  },
  .vip_port_cfg = {
   .ctrlChanSel = VPS_VIP_CTRL_CHAN_SEL_15_8,
   .ancChSel8b = VPS_VIP_ANC_CH_SEL_DONT_CARE,
   .pixClkEdgePol = VPS_VIP_PIX_CLK_EDGE_POL_RISING,
   .invertFidPol = 0,
   .embConfig = {
    .errCorrEnable = 1,
    .srcNumPos = VPS_VIP_SRC_NUM_POS_DONT_CARE,
    .isMaxChan3Bits = 0,
   },
   .disConfig = {
    .fidSkewPostCnt = 0,
    .fidSkewPreCnt = 0,
    .lineCaptureStyle =
     VPS_VIP_LINE_CAPTURE_STYLE_DONT_CARE,
    .fidDetectMode =
     VPS_VIP_FID_DETECT_MODE_DONT_CARE,
    .actvidPol = VPS_VIP_POLARITY_DONT_CARE,
    .vsyncPol =  VPS_VIP_POLARITY_DONT_CARE,
    .hsyncPol = VPS_VIP_POLARITY_DONT_CARE,
   }
  },
  .video_capture_mode =
     VPS_CAPT_VIDEO_CAPTURE_MODE_SINGLE_CH_NON_MUX_EMBEDDED_SYNC,
  .video_if_mode = VPS_CAPT_VIDEO_IF_MODE_16BIT,
  .input_data_format = FVID2_DF_YUV422P,
 },
};

Hi Ralph,thanks for your reply.

Attached file is our video pin schematic.please check it.

Any suggestions please let me know.

thanks a lot.

Hi Ralph,

I have look at your "Capturing second HD input."

and change 1 to 2  in "for (i = 0; i < 1; i++)" .

now we can find vip1 instance

==========================

Starting system message bus: dbus.
Starting telnet daemon.
Starting syslogd/klogd: done
Starting thttpd.
Starting PVR
Starting Matrix GUI application.
i am in matrix-gui-e 22222!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
Stopping Matrix GUI application.
Stopping PVR
ti81xx_vidout_probe ok!!!!!
insmod ti81xxvo done
insmod ti81xxvin done
tvp7002_probe 111111
tvp7002_probe 222222
tvp7002_probe 333333
tvp7002 2-0021: tvp7002 found @ 0x21 (OMAP I2C adapter)
error:0
tvp7002_probe 444444
tvp7002 2-0021: Rev. 04 detected.
tvp7002 2-0021: Write: retry ... 0
tvp7002 2-0021: Write: retry ... 1
tvp7002 2-0021: Write: retry ... 2
tvp7002 2-0021: Write: retry ... 3
tvp7002 2-0021: Write: retry ... 4
tvp7002 2-0021: TVP7002 write error -121 at reg:f
OK registering v4l2 subdevice
ti81xxvin ti81xxvin: registered sub device tvp7002
tvp7002_probe 111111
tvp7002_probe 222222
tvp7002_probe 333333
tvp7002 2-005c: tvp7002 found @ 0x5c (OMAP I2C adapter)
tvp7002 2-005c: TVP7002 read error -121 at reg:11
error:0
tvp7002_probe 444444
tvp7002 2-005c: Rev. 04 detected.
OK registering v4l2 subdevice
ti81xxvin ti81xxvin: registered sub device tvp7002
ti81xxvin ti81xxvin: TI81xx HDVPSS Capture driver initialized

========================================================

but "port a overflow" is still exiting.

Sorry, I've never seen the overflow error that you're getting. If it helps, I found that using active ID sync helped me capture video data.

Ralph

we use embedded 16bit yuv422 video as vip1's input.

any idea will be appreicated.

please can someone help us to check whether we need to modify pinmux settings?

board-ti8168.c

static struct omap_board_mux board_mux[] __initdata = {

 /* PIN mux for non-muxed NOR */
 TI816X_MUX(TIM7_OUT, OMAP_MUX_MODE1), /* gpmc_a12 */
 TI816X_MUX(UART1_CTSN, OMAP_MUX_MODE1), /* gpmc_a13 */
 TI816X_MUX(UART1_RTSN, OMAP_MUX_MODE1), /* gpmc_a14 */
 TI816X_MUX(UART2_RTSN, OMAP_MUX_MODE1), /* gpmc_a15 */
 /* REVISIT: why 2 lines configured as gpmc_a15 */
 TI816X_MUX(SC1_RST, OMAP_MUX_MODE1), /* gpmc_a15 */
 TI816X_MUX(UART2_CTSN, OMAP_MUX_MODE1), /* gpmc_a16 */
 TI816X_MUX(UART0_RIN, OMAP_MUX_MODE1), /* gpmc_a17 */
 TI816X_MUX(UART0_DCDN, OMAP_MUX_MODE1), /* gpmc_a18 */
 TI816X_MUX(UART0_DSRN, OMAP_MUX_MODE1), /* gpmc_a19 */
 TI816X_MUX(UART0_DTRN, OMAP_MUX_MODE1), /* gpmc_a20 */
 TI816X_MUX(SPI_SCS3, OMAP_MUX_MODE1), /* gpmc_a21 */
 TI816X_MUX(SPI_SCS2, OMAP_MUX_MODE1), /* gpmc_a22 */
 TI816X_MUX(GP0_IO6, OMAP_MUX_MODE2), /* gpmc_a23 */
 TI816X_MUX(TIM6_OUT, OMAP_MUX_MODE1), /* gpmc-a24 */
 TI816X_MUX(SC0_DATA, OMAP_MUX_MODE1), /* gpmc_a25 */
 /* for controlling high address */
 TI816X_MUX(GPMC_A27, OMAP_MUX_MODE1), /* gpio-20 */
 
#if 1//for vip1 input   added

 TI816X_MUX(TSI1_DCLK, 0x1A),      //VIN[1]A_D[9]
 TI816X_MUX(TSI1_DATA, 0x1A),      //VIN[1]A_D[10]
 TI816X_MUX(TSI1_BYTSTRT, 0x1A),  //VIN[1]A_D[11]
 TI816X_MUX(TSI1_PACVAL, 0x1A),  //VIN[1]A_D[12]
 TI816X_MUX(TSI1_PACERR, 0x1A),  //VIN[1]A_D[13]
 TI816X_MUX(TSI2_DCLK, 0x19),   //VIN[1]A_D[14]
 
 TI816X_MUX(TSI3_DCLK, 0x1A),   //VIN[1]A_D[4]
 TI816X_MUX(TSI3_DATA, 0x1A),  //VIN[1]A_D[5]
 TI816X_MUX(TSI3_BYTSTRT, 0x1A),  //VIN[1]A_D[6]
 TI816X_MUX(TSI3_PACVAL, 0x1A),  //VIN[1]A_D[7]
 TI816X_MUX(TSI3_PACERR, 0x1A),  //VIN[1]A_D[8]
 TI816X_MUX(TSI4_DCLK, 0x1A),   //VIN[1]A_D[15]
 
 TI816X_MUX(TSO1_DCLK, 0x1A),  //VIN[1]A_CLK
 
 TI816X_MUX(TSO1_DATA, 0x1A),  //VIN[1]A_D[0]
 TI816X_MUX(TSO1_BYTSTRT, 0x1A), //VIN[1]A_D[1]
 TI816X_MUX(TSO1_PACVAL, 0x1A),  //VIN[1]A_D[2]
 TI816X_MUX(TSO1_PACERR, 0x1A),  //VIN[1]A_D[3]
#endif
 

 
 { .reg_offset = OMAP_MUX_TERMINATOR },
};

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/189208.aspx?pi36418=2

Ah I understand. IIRC, the default TI pin mux settings worked for us for VIP0, VIP1, DVO2 but not DVO1 (DVO1 is linked to HDMI).

If you want DVO1 to output video, you must lose VIP1 functionality and change the pin mux settings. This is because some DVO1 pins are shared with VIP1 pins.

--Ralph

========================

We use DVO2 to output video.I read your reply,and I think we don't need to set pinmux settings,is it right?

Do we need mask those lines as below:

ti81xx_vpss.c-> ti81xx_init_vpss-> //retval += ti81xx_hdmi_init();

dm8168_root_fs/etc/init.d/load-hd-firmware.sh  -->#modprobe ti81xxhdmi

and change "modprobe vpss sbufaddr=0xBFB00000 mode=hdmi:1080p-60,dvo2:1080p-60,hdcomp:1080p-60 i2c_mode=1"

 to "modprobe vpss sbufaddr=0xBFB00000 mode=dvo2:1080p-60 i2c_mode=1"

==============

if someone knows,could you please tell me .

thanks a lot.

It should just work for DVO2.

All you should need to do apart from modifying output format settings in your OpenMAX app is "echo 1:dvo2 > /sys/devices/platform/vpss/graphics0/nodes". Don't change the modprobe line, there's no need.

Ralph

Hi Ralph,

I am trying to do 8-bit bt.656 video capture on VIP1 PORTB using OMX application . I can see the video is getting detected in the VIP Parser block which confirms that bt.656 stream is coming to the VIP1 PORTB .

The problem is that OMX VFCC is not able to capture frames ,the FVID2_dequeue call is not returning frames . I am able to capture bt.656 stream on VIP0 PORTA . Have you faced similar problems when capturing 8-bit bt.656 stream on VIP1 PORTB  using OMX application ?

Can you give me any suggestions ?where i can look into in OMX framework for the PORTB capture to work ?

Thanks,

Siva .

I've never captured on a sub-port I'm afraid. I've only ever done 24 bit on VIP1 or 16 bit on VIP0.

All I can suggest is if you're using the capture_encode demo try changing src/ilclient_utils.c specifically paramPort.format.video.eColorFormat and friends.

Ralph

TI81XX_VPSS_Video_Driver_User_Guide.pdf, page 10

Is DVO2 mapped to "/dev/video1"?

Is HDMI/DVO1 mapped to "/dev/video2"?

SD and HDCOMP are mapped to "/dev/video3"?

Hi,

All displays are independent of video nodes. Any of the video nodes that is /dev/video1 and /dev/video2 can be connected to any of the displays. /dev/video2 can be connected only to SD display.

Hi Ralf,

I have below doubt in VIP input format settings.

I need to configure VIP0 PORTA 24 bit mode and PORTB with 16 bit mode is this possible.

Or I have to configure VIP0 one port input format 24 bit and VIP1 one port 16 bit, which will work?

This support is present in TI VPSS driver ?

Can you please clarify this doubt.

Thanks and Regards,

Nithin

VIP0 can support at max 24bit input and vip1 16bit input, so it is possible and supported by VPSS drivers.

Regards,

Brijesh

Hi Nithin, you have to use just one port per input if you want 16 and 24 bit.

So you have 24 bit on port A of VIP0 and 16 bit on port A of VIP1.

I've never tried getting capture working simultaneously on both VIPs but I have seen it working individually on each VIP. Hope this helps,

Ralph

Hi Ralph and Brijesh,

Thanks for the information.

Thanks and Regards,

Nithin