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Ha all,
I'm using the DM8168 device and I have to use McASP1 port in trasmission mode using data port, but in documentation I don't find the right address to use for write data port (XBUF data port register. See TMS320DM816x DaVinci Video Processors Technical Reference Manual - sprugx8.pdf Table 14-8).
Can some one help me?
Bye bye
Paolo.
Hi Paolo,
McASP1 XBUFn (n = 0 to 5) register can be accessed from both data port (DAT) and configuration port (CFG). You can select from which port through programming the XFMT register (at offset 0xA8). To select the data port, you need to clear bit XFMT[3] XBUSEL to 0x0. Then if you need to write a value in the McASP1 XBUF0 register, you can do this in address 0x46400200.
Regards,
Pavel
Thanks a lot, Pavel, for your answer,
I will try in few minutes.
Every way, can you tell me where are these informations and in which doc file? So in future I will find it myself :-)
bye
Paolo.
Hi,
things are a bit 'more complicated.
I'm already successfully using mcasp0 in TX, with the EDMA writes on port XBUF0 (0x4803C200). I would however need to activate the fifo so as not to risk going in Underrun.
So the first step is to clear bit XFMT[3] XBUSEL to 0x0. After this, everything stop working, and McASP1 TX goes in underun. I think the problem is because i write data at a wrong address (0x4803C200 and 0x46400200 doesn't work). I am using DSP (not cortex) processor.
Any other ideas?
Bye Paolo.
Hi Paolo,
All this information is available in the DM816x TRM.
"McASP1 XBUFn (n = 0 to 5) register can be accessed from both data port (DAT) and configuration port (CFG)." See section 14.2.8.1 Data Transmission and Reception.
"You can select from which port through programming the XFMT register (at offset 0xA8). To select the data port, you need to clear bit XFMT[3] XBUSEL to 0x0." See NOTE and last sentence in section 14.2.8.1.2 Transfers Through the Data Port (DAT). Also see NOTE and last sentence in section 14.2.8.1.3 Transfers Through the Configuration Bus (CFG).
The base address of the McASP1 (data port) is documented in Table 1-11. L3 Memory Map, and the XBUF0 offset is documented in section Table 14-7. McASP Registers Accessed Through Configuration Bus. The table 14-7 title is not very appropriate, as per my understanding this register map is valid for the Data bus also.
Regards,
Pavel
We have also some information in the DM816x Datasheet.
Check Table 8-78. McASP Registers Accessed Through DAT Port.
Can you try with XBUF address 0x01D02000 or 0x01D06000 ?
Best Regards,
Pavel
Sorry if something is still not clear to me.
The addresses that I'm looking for are those that are missing in the document TMS320DM816x DaVinci Video Processors Technical Reference Manual - sprugx8.pdf, Table 14-8.
When I clear bit XFMT[3] XBUSEL to 0x0, I have to write in the XBUF register that is at a different address than the XBUF0 (BASE ADDRESS + 0x0200) (that I use in 'Confuguration BUS' mode with XFMT[3] XBUSEL to 0x1).
All this is necessary (I belive) for the target that is to use the McASP FIFO.
Any other suggestion?
Thanks a lot for your time.
Paolo.
Unfortunately the two addresses given do not seem to work. However, Table 8-78 in my document (TMS320DM816x DaVinci Digital Media Processors (Rev. B) - sprs614b.pdf) is regarding: 'Table 8-78. Timing Requirements for McASP' ... Are we refering to the same document or we have different revision? Where did you find address 0x01D02000 and 0x01D06000?
Everyway, As I said, my final goal is to use MCASP1 FIFO, by the setting: MCASP1_WFIFOCTL = 0x00010202; (with 2 tx serializer)
So, I don't know where to write to put data into the FIFO.
Every attempt, McASP goes in underun.
Any other suggestion?
Thanks a lot for your time.
Paolo
Hi Paolo,
I am using newer version of the DM816x data sheet (SPRS614C – MARCH 2011 – REVISED OCTOBER 2012). This version will be up uploaded soon in the TI web site.
Let us first verify that the problem is in the XBUFn registers address from the perspective of the Data port. Can you try if your use-case will work properly with the XBUFn registers accessed from the Data port, but without enabling the McASP1 Audio FIFO (WFIFOCTL = 0) ?
Regards,
Pavel
Hi Pavel,
I also thought like you. I already tried with the FIFO disabled and attempting to transmit in data port mode, but unfortunately without success. I always have underun. Like if I don't write in the right register.
Thanks.
Bye. Paolo.
Hi Paolo,
Can you share your source code (at least the part that I can re-create the underrun) , I want to make a closer look/check.
Meanwhile, can you try with the 0x01D06200 address (or 0x01D02200)? Reading again the new version of the Data Sheet, I suspect that 0x01D06000 can be a base address.
Best Regards,
Pavel
#define DATAPORT 1
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/hal/Hwi.h>
#include "evm816x_mcasp.h"
#include "evm816x_i2c.h"
#include "edma3.h"
#include "cslr_edma3cc_m.h"
#include "adau1966.h"
#include "cs5368.h"
#include <ti/sysbios/family/c64p/Cache.h>
#include "appconfig.h"
#include "SignalProc.h"
#include "global.h"
#include "tools.h"
void testInOutEDMA_SetMCASP(void);
void testInOutEDMA_StartMCASP(void);
void testInOutEDMA_setup_edmaRx(void);
void testInOutEDMA_setup_edmaTx(void);
void testInOutEDMA_isr_init(void);
void testInOutEDMA_start_edma(void);
#define REGS_BASE 0x49000000
#define PARAM_BASE 0x49004000
#define EDMA_CHANNEL_AREVT0 (9) // McASP0_RX event
#define EDMA_CHANNEL_RX_PING (128)
#define EDMA_CHANNEL_RX_PONG (129)
#define EDMA_CHANNEL_AXEVT1 (10) // McASP1_TX event
#define EDMA_CHANNEL_TX_PING (130)
#define EDMA_CHANNEL_TX_PONG (131)
static CSL_Edma3ccRegs *edma3Regs = (CSL_Edma3ccRegs *) REGS_BASE;
#pragma DATA_ALIGN(bufferRx,64);
int32_t bufferRx[2][NUM_CH_IN*PROC_BUFF_SAMPLE_LEN];
#pragma DATA_ALIGN(bufferTx,64);
int32_t bufferTx[2][TDM_OUT_NUM_CH*PROC_BUFF_SAMPLE_LEN*OUT_OVER_SAMPLING];
static int inSampleCounter = 0;
static int32_t *inSamplePointer;
static int outSampleCounter = 0;
static int32_t *outSamplePointer = &bufferTx[0][NUM_CH_OUT];
static Void testInOutEDMA_edma_isr(unsigned int dummy)
{
do
{
if( edma3Regs->SHADOW[1].IPR & (1<< EDMA_CHANNEL_AREVT0))
{
MCASP0_PDSET = 0x02000000;
// clear IPR flag
edma3Regs->SHADOW[1].ICR |= (1 << EDMA_CHANNEL_AREVT0);
int bufferIndex;
if(edma3Regs->PARAMSET[EDMA_CHANNEL_AREVT0].DST >= (Uint32)bufferRx[1])
bufferIndex = 0;
else
bufferIndex = 1;
#warn Cache_inv(bufferRx[bufferIndex],sizeof(bufferRx[bufferIndex]),Cache_Type_ALL,1);
SignalProc_Process(bufferRx[bufferIndex], bufferTx[bufferIndex]);
Cache_wb(bufferTx[bufferIndex],sizeof(bufferTx[bufferIndex]),Cache_Type_ALL,0);
MCASP0_PDCLR = 0x02000000;
}
if( edma3Regs->SHADOW[1].IPR & (1<< EDMA_CHANNEL_AXEVT1))
{
if(edma3Regs->PARAMSET[EDMA_CHANNEL_AXEVT1].SRC >= (Uint32)bufferTx[1])
{
}
else
{
outSampleCounter = 1;
outSamplePointer = &bufferTx[0][ outSampleCounter * (OUT_OVER_SAMPLING*TDM_OUT_NUM_CH) ];
inSampleCounter = 2 * PROC_BUFF_SAMPLE_LEN - 1;
inSamplePointer = &bufferRx[1][NUM_CH_IN*(PROC_BUFF_SAMPLE_LEN - 1)];
}
// clear IPR flag
edma3Regs->SHADOW[1].ICR |= (1 << EDMA_CHANNEL_AXEVT1);
}
} while (edma3Regs->SHADOW[1].IPR);
}
static Void testInOutEDMA_mcAsp_isr(unsigned int dummy)
{
static int32_t prevVal[NUM_CH_OUT];
int32_t outSampleLowLatency[NUM_CH_OUT];
MCASP1_PDSET = 0x02000000;
// Cache_inv(outSamplePointer,OUT_OVER_SAMPLING*TDM_OUT_NUM_CH * sizeof(int32_t),Cache_Type_ALL,0);
Cache_inv(inSamplePointer,NUM_CH_IN * sizeof(int32_t),Cache_Type_ALL,0);
outSampleLowLatency[IDX_OUT_TABLE_CH_0] = inSamplePointer[1];
outSampleLowLatency[IDX_OUT_TABLE_CH_1] = inSamplePointer[2];
outSampleLowLatency[IDX_OUT_TABLE_CH_2] = inSamplePointer[3];
outSampleLowLatency[IDX_OUT_TABLE_CH_3] = inSamplePointer[4];
outSampleLowLatency[IDX_OUT_TABLE_CH_4] = inSamplePointer[5];
outSampleLowLatency[IDX_OUT_TABLE_CH_5] = inSamplePointer[6];
outSampleLowLatency[IDX_OUT_TABLE_CH_6] = inSamplePointer[7];
outSampleLowLatency[IDX_OUT_TABLE_CH_7] = inSamplePointer[0];
#if(OUT_OVER_SAMPLING == 2)
int32_t val,prevV,diff;
int32_t *outPtr;
float aux;
outPtr = &outSamplePointer[0]; val = outSampleLowLatency[0]; prevV = prevVal[0];
diff = val-prevV;
*(outPtr) += prevV + diff/OUT_OVER_SAMPLING; outPtr += TDM_OUT_NUM_CH;
*(outPtr) += val;
prevVal[0] = val;
outPtr = &outSamplePointer[1]; val = outSampleLowLatency[1]; prevV = prevVal[1];
diff = val-prevV;
*(outPtr) += prevV + diff/OUT_OVER_SAMPLING; outPtr += TDM_OUT_NUM_CH;
*(outPtr) += val;
prevVal[1] = val;
outPtr = &outSamplePointer[2]; val = outSampleLowLatency[2]; prevV = prevVal[2];
diff = val-prevV;
*(outPtr) += prevV + diff/OUT_OVER_SAMPLING; outPtr += TDM_OUT_NUM_CH;
*(outPtr) += val;
prevVal[2] = val;
outPtr = &outSamplePointer[3]; val = outSampleLowLatency[3]; prevV = prevVal[3];
diff = val-prevV;
*(outPtr) += prevV + diff/OUT_OVER_SAMPLING; outPtr += TDM_OUT_NUM_CH;
*(outPtr) += val;
prevVal[3] = val;
outPtr = &outSamplePointer[4]; val = outSampleLowLatency[4]; prevV = prevVal[4];
diff = val-prevV;
*(outPtr) += prevV + diff/OUT_OVER_SAMPLING; outPtr += TDM_OUT_NUM_CH;
*(outPtr) += val;
prevVal[4] = val;
outPtr = &outSamplePointer[5]; val = outSampleLowLatency[5]; prevV = prevVal[5];
diff = val-prevV;
*(outPtr) += prevV + diff/OUT_OVER_SAMPLING; outPtr += TDM_OUT_NUM_CH;
*(outPtr) += val;
prevVal[5] = val;
outPtr = &outSamplePointer[6]; val = outSampleLowLatency[6]; prevV = prevVal[6];
diff = val-prevV;
*(outPtr) += prevV + diff/OUT_OVER_SAMPLING; outPtr += TDM_OUT_NUM_CH;
*(outPtr) += val;
prevVal[6] = val;
outPtr = &outSamplePointer[7]; val = outSampleLowLatency[7]; prevV = prevVal[7];
diff = val-prevV;
*(outPtr) += prevV + diff/OUT_OVER_SAMPLING; outPtr += TDM_OUT_NUM_CH;
*(outPtr) += val;
prevVal[7] = val;
#else
#error OUT_OVER_SAMPLING must be equal 2
#endif
Cache_wb(outSamplePointer,OUT_OVER_SAMPLING*TDM_OUT_NUM_CH * sizeof(int32_t),Cache_Type_ALL,0);
outSamplePointer += TDM_OUT_NUM_CH*OUT_OVER_SAMPLING;
if(++outSampleCounter >= PROC_BUFF_SAMPLE_LEN*2)
{
outSampleCounter = 0;
outSamplePointer = (int32_t *)bufferTx;
}
inSamplePointer += NUM_CH_IN;
if(++inSampleCounter >= PROC_BUFF_SAMPLE_LEN*2)
{
inSampleCounter = 0;
inSamplePointer = (int32_t *)bufferRx;
}
MCASP0_RSTAT = 0x00000040;
MCASP1_PDCLR = 0x02000000;
}
void testInOutEDMA_MainProcess(void)
{
I2C0_CLOCK_ENABLE;
MCASP0_CLOCK_ENABLE;
MCASP1_CLOCK_ENABLE;
MCASP2_CLOCK_ENABLE;
dspPrintf("SignalProc_Init");
SignalProc_Init();
dspPrintf("testInOutEDMA_SetMCASP");
testInOutEDMA_SetMCASP();
// dspPrintf("cs5368_Init");
// cs5368_Init();
dspPrintf("adau1966_Init");
adau1966_Init();
dspPrintf("testInOutEDMA_setup_edmaRx");
testInOutEDMA_setup_edmaRx();
dspPrintf("testInOutEDMA_setup_edmaTx");
testInOutEDMA_setup_edmaTx();
dspPrintf("testInOutEDMA_isr_init");
testInOutEDMA_isr_init();
dspPrintf("testInOutEDMA_start_edma");
testInOutEDMA_start_edma();
dspPrintf("testInOutEDMA_StartMCASP");
testInOutEDMA_StartMCASP();
while(1)
{
Cache_Size size;
dspPrintf("LOOP. MCASP0_RSTAT=0x%08X MCASP1_XSTAT=0x%08X MCASP1_WFIFOSTS=0x%08X",MCASP0_RSTAT,MCASP1_XSTAT,MCASP1_WFIFOSTS & 0xFF);
Task_sleep(10000);
Cache_getSize(&size);
}
}
void testInOutEDMA_SetMCASP(void)
{
//////////////////////////
//MCASP0 - CS5368
//////////////////////////
MCASP0_GBLCTL = 0; // Reset
MCASP0_RGBLCTL = 0; // Reset RX
MCASP0_XGBLCTL = 0; // Reset TX
/* RX */
MCASP0_RMASK = 0xffffffff; // No padding used
MCASP0_RFMT = 0x000180F8; // MSB 16bit, 1-delay (For I2S), no pad, CFGBus
MCASP0_AFSRCTL = 0x00000412; // 2-slot TDM, Falling edge (Left channel low), INTERNAL FS, Width:word
MCASP0_ACLKRCTL = 0x00000080; // Rising edge, INTERNAL CLK (from tx side)
MCASP0_AHCLKRCTL = (((48000*16)/FS)) - 1;
MCASP0_RTDM = 0x000000FF; // Slots 0 & 1 used
MCASP0_RINTCTL = 0x00000080; // RSTAFRM
MCASP0_RCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256
/* TX */
MCASP0_XMASK = 0xffffffff; // No padding used
MCASP0_XFMT = 0x000180F8; // MSB 16bit, 1-delay, no pad, CFGBus
MCASP0_AFSXCTL = 0x00000412; // 2-slot TDM, Falling edge (Left channel low), INTERNAL FS, Width:word
MCASP0_ACLKXCTL = 0x00000040; // Transmit/Receive sync, Rising edge, INTERNAL CLK , Div-by-16
MCASP0_AHCLKXCTL = 0x0000000F; // EXTERNAL CLK, div-by-1
MCASP0_XTDM = 0x00000001; // Slots 0 & 1 used
MCASP0_XINTCTL = 0x00000000; // Not used
MCASP0_XCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256
MCASP0_SRCTL0 = 0x000E; // MCASP0.AXR0
MCASP0_PFUNC = 0x02000000; // All MCASPs
MCASP0_PDIR = 0xE2000000; // All inputs except
MCASP0_DITCTL = 0x00000000; // Not used
MCASP0_DLBCTL = 0x00000000; // Not used
MCASP0_AMUTE = 0x00000000; // Not used
/* Starting sections of the McASP*/
MCASP0_XGBLCTL |= GBLCTL_XHCLKRST_ON; // TX HS Clk
while ( ( MCASP0_XGBLCTL & GBLCTL_XHCLKRST_ON ) != GBLCTL_XHCLKRST_ON );
MCASP0_RGBLCTL |= GBLCTL_RHCLKRST_ON; // RX HS Clk
while ( ( MCASP0_RGBLCTL & GBLCTL_RHCLKRST_ON ) != GBLCTL_RHCLKRST_ON );
MCASP0_XGBLCTL |= GBLCTL_XCLKRST_ON; // TX Clk
while ( ( MCASP0_XGBLCTL & GBLCTL_XCLKRST_ON ) != GBLCTL_XCLKRST_ON );
MCASP0_RGBLCTL |= GBLCTL_RCLKRST_ON; // RX Clk
while ( ( MCASP0_RGBLCTL & GBLCTL_RCLKRST_ON ) != GBLCTL_RCLKRST_ON );
//////////////////////////
//MCASP1 - DA adau1966
//////////////////////////
MCASP1_GBLCTL = 0; // Reset
MCASP1_RGBLCTL = 0; // Reset RX
MCASP1_XGBLCTL = 0; // Reset TX
// RX
MCASP1_RMASK = 0xffffffff; // No padding used
MCASP1_RFMT = 0x000180F8; // MSB 32bit, 1-delay, no pad, CFGBus
MCASP1_AFSRCTL = 0x00000412; // 8-slot TDM, Falling edge (Left channel low), INTERNAL FS, Width:word
MCASP1_ACLKRCTL = 0x00000080; // Rising edge, INTERNAL CLK (from tx side)
MCASP1_AHCLKRCTL = 0x0000000F; // INT CLK (from tx side) divide by 8 --> 24.576MHz
MCASP1_RTDM = 0x00000001; // Slots 0 & 1 used
MCASP1_RINTCTL = 0x00000000; // Not used
MCASP1_RCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256
// TX
MCASP1_XMASK = 0xffffffff; // No padding used
#if DATAPORT == 0
MCASP1_XFMT = 0x000180F8; // MSB 32bit, 1-delay, no pad, CFGBus
#else
MCASP1_XFMT = 0x000180F0; // MSB 32bit, 1-delay, no pad, DataBus
#endif
MCASP1_AFSXCTL = 0x00000213; // 4-slot TDM, Falling edge (Left channel low), INTERNAL FS, Width:word
MCASP1_ACLKXCTL = 0x00000040; // Transmit/Receive async, Rising edge, INTERNAL CLK ,
MCASP1_AHCLKXCTL = (((48000*32)/FS)/OUT_OVER_SAMPLING) - 1;
MCASP1_XTDM = 0x000000FF; // Slots 0-7 used
MCASP1_XINTCTL = 0x00000000; // Not used
MCASP1_XCLKCHK = 0x00FF0008; // 255-MAX 0-MIN, div-by-256
MCASP1_SRCTL0 = 0x000D; // Serializer is in trasmit
MCASP1_SRCTL1 = 0x000D; // Serializer is in trasmit
MCASP1_PFUNC = 0x02000000; // All MCASPs except AMUTE
MCASP1_PDIR = 0x1E000003; // All inputs except AFSX, AHCLKX, ACLKX, AXR1, AXR0
MCASP1_DITCTL = 0x00000000; // Not used
MCASP1_DLBCTL = 0x00000000; // Not used
MCASP1_AMUTE = 0x00000000; // Not used
// MCASP1_WFIFOCTL = 0x00010202;
// Starting sections of the McASP
MCASP1_XGBLCTL |= GBLCTL_XHCLKRST_ON; // TX HS Clk
while ( ( MCASP1_XGBLCTL & GBLCTL_XHCLKRST_ON ) != GBLCTL_XHCLKRST_ON );
MCASP1_RGBLCTL |= GBLCTL_RHCLKRST_ON; // RX HS Clk
while ( ( MCASP1_RGBLCTL & GBLCTL_RHCLKRST_ON ) != GBLCTL_RHCLKRST_ON );
MCASP1_XGBLCTL |= GBLCTL_XCLKRST_ON; // TX Clk
while ( ( MCASP1_XGBLCTL & GBLCTL_XCLKRST_ON ) != GBLCTL_XCLKRST_ON );
MCASP1_RGBLCTL |= GBLCTL_RCLKRST_ON; // RX Clk
while ( ( MCASP1_RGBLCTL & GBLCTL_RCLKRST_ON ) != GBLCTL_RCLKRST_ON );
}
void testInOutEDMA_StartMCASP(void)
{
//////////////////////////
//MCASP0 - CS5368
//////////////////////////
MCASP0_XSTAT = 0x0000ffff; // Clear all
MCASP0_RSTAT = 0x0000ffff; // Clear all
MCASP0_XGBLCTL |= GBLCTL_XSRCLR_ON; // TX Serializer
while ( ( MCASP0_XGBLCTL & GBLCTL_XSRCLR_ON ) != GBLCTL_XSRCLR_ON );
MCASP0_RGBLCTL |= GBLCTL_RSRCLR_ON; // RX Serializer
while ( ( MCASP0_RGBLCTL & GBLCTL_RSRCLR_ON ) != GBLCTL_RSRCLR_ON );
/* Write a 0, so that no underrun occurs after releasing the state machine */
MCASP0_XBUF0 = 0;
MCASP0_RBUF0 = 0;
MCASP0_XGBLCTL |= GBLCTL_XSMRST_ON; // TX State Machine
while ( ( MCASP0_XGBLCTL & GBLCTL_XSMRST_ON ) != GBLCTL_XSMRST_ON );
MCASP0_RGBLCTL |= GBLCTL_RSMRST_ON; // RX State Machine
while ( ( MCASP0_RGBLCTL & GBLCTL_RSMRST_ON ) != GBLCTL_RSMRST_ON );
//////////////////////////
//MCASP1 - DA adau1966
//////////////////////////
MCASP1_XSTAT = 0x0000ffff; // Clear all
MCASP1_RSTAT = 0x0000ffff; // Clear all
MCASP1_XGBLCTL |= GBLCTL_XSRCLR_ON; // TX Serializer
while ( ( MCASP1_XGBLCTL & GBLCTL_XSRCLR_ON ) != GBLCTL_XSRCLR_ON );
MCASP1_RGBLCTL |= GBLCTL_RSRCLR_ON; // RX Serializer
while ( ( MCASP1_RGBLCTL & GBLCTL_RSRCLR_ON ) != GBLCTL_RSRCLR_ON );
// Write a 0, so that no underrun occurs after releasing the state machine
MCASP1_XBUF0 = 0;
// MCASP1_RBUF0 = 0;
MCASP1_XBUF1 = 0;
// MCASP1_RBUF1 = 0;
MCASP1_XGBLCTL |= GBLCTL_XSMRST_ON; // TX State Machine
while ( ( MCASP1_XGBLCTL & GBLCTL_XSMRST_ON ) != GBLCTL_XSMRST_ON );
MCASP1_RGBLCTL |= GBLCTL_RSMRST_ON; // RX State Machine
while ( ( MCASP1_RGBLCTL & GBLCTL_RSMRST_ON ) != GBLCTL_RSMRST_ON );
//I Sync devono partire tutti insieme !!
MCASP0_XGBLCTL |= GBLCTL_XFRST_ON; // TX Frame Sync
MCASP1_XGBLCTL |= GBLCTL_XFRST_ON; // TX Frame Sync
MCASP0_RGBLCTL |= GBLCTL_RFRST_ON; // RX Frame Sync
MCASP1_RGBLCTL |= GBLCTL_RFRST_ON; // RX Frame Sync
while ( ( MCASP0_XGBLCTL & GBLCTL_XFRST_ON ) != GBLCTL_XFRST_ON );
while ( ( MCASP1_XGBLCTL & GBLCTL_XFRST_ON ) != GBLCTL_XFRST_ON );
while ( ( MCASP0_RGBLCTL & GBLCTL_RFRST_ON ) != GBLCTL_RFRST_ON );
while ( ( MCASP1_RGBLCTL & GBLCTL_RFRST_ON ) != GBLCTL_RFRST_ON );
}
void testInOutEDMA_setup_edmaRx(void)
{
static CSL_Edma3ParamSetup *myParamSetup_base;
static CSL_Edma3ParamSetup *myParamSetup_ping;
static CSL_Edma3ParamSetup *myParamSetup_pong;
edma3Regs = (CSL_Edma3ccRegs *) REGS_BASE;
// assegnamo il canale alla regione 1 (dsp).
edma3Regs->DRA[1].DRAE = (1 << EDMA_CHANNEL_AREVT0);
// Link the mcbsp tx event to this parameter table
edma3Regs->DCHMAP[EDMA_CHANNEL_AREVT0] = (PARAM_BASE + (EDMA_CHANNEL_AREVT0 * 0x20));
myParamSetup_base = (CSL_Edma3ParamSetup *) (PARAM_BASE + (EDMA_CHANNEL_AREVT0 * 0x20)) ; // base table, linked to the synch event
myParamSetup_ping = (CSL_Edma3ParamSetup *) (PARAM_BASE + (EDMA_CHANNEL_RX_PING * 0x20)) ; // reload ping table
myParamSetup_pong = (CSL_Edma3ParamSetup *) (PARAM_BASE + (EDMA_CHANNEL_RX_PONG * 0x20)) ; // reload pong table
// SETUP BASE TABLE
myParamSetup_base->option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN,\
EDMA_CHANNEL_AREVT0, // TCC_CODE
CSL_EDMA3_TCC_NORMAL,\
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_DIS, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR);
myParamSetup_base->srcAddr = 0x48038000 + 0x280; //MCASP0_RBUF0_32BIT
myParamSetup_base->dstAddr = (Uint32)bufferRx[0];
myParamSetup_base->aCntbCnt = CSL_EDMA3_CNT_MAKE(4,NUM_CH_IN*PROC_BUFF_SAMPLE_LEN);
myParamSetup_base->srcDstBidx = CSL_EDMA3_BIDX_MAKE(0,4); // increment source by 4, don't increment destination
myParamSetup_base->linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE (EDMA_CHANNEL_RX_PONG * 0x20, 1); // link table -> pong
myParamSetup_base->srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0);
myParamSetup_base->cCnt = 1;
// SETUP PING TABLE, SAME AS BASE
myParamSetup_ping->option = myParamSetup_base->option;
myParamSetup_ping->srcAddr = myParamSetup_base->srcAddr;
myParamSetup_ping->dstAddr = myParamSetup_base->dstAddr;
myParamSetup_ping->aCntbCnt = myParamSetup_base->aCntbCnt;
myParamSetup_ping->srcDstBidx = myParamSetup_base->srcDstBidx;
myParamSetup_ping->linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE (EDMA_CHANNEL_RX_PONG * 0x20, 1);
myParamSetup_ping->srcDstCidx = myParamSetup_base->srcDstCidx;
myParamSetup_ping->cCnt = myParamSetup_base->cCnt;
// SETUP PONG TABLE, SAME AS BASE BUT DIFFERENT SOURCE ADDRESS
myParamSetup_pong->option = myParamSetup_base->option;
myParamSetup_pong->srcAddr = myParamSetup_base->srcAddr;
myParamSetup_pong->dstAddr = (Uint32)bufferRx[1];
myParamSetup_pong->aCntbCnt = myParamSetup_base->aCntbCnt;
myParamSetup_pong->srcDstBidx = myParamSetup_base->srcDstBidx;
myParamSetup_pong->linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE (EDMA_CHANNEL_RX_PING * 0x20, 1);
myParamSetup_pong->srcDstCidx = myParamSetup_base->srcDstCidx;
myParamSetup_pong->cCnt = myParamSetup_base->cCnt;
}
void testInOutEDMA_setup_edmaTx(void)
{
static CSL_Edma3ParamSetup *myParamSetup_base;
static CSL_Edma3ParamSetup *myParamSetup_ping;
static CSL_Edma3ParamSetup *myParamSetup_pong;
edma3Regs = (CSL_Edma3ccRegs *) REGS_BASE;
// assegnamo il canale alla regione 1 (dsp).
edma3Regs->DRA[1].DRAE |= (1 << EDMA_CHANNEL_AXEVT1);
// Link the mcbsp tx event to this parameter table
edma3Regs->DCHMAP[EDMA_CHANNEL_AXEVT1] = (PARAM_BASE + (EDMA_CHANNEL_AXEVT1 * 0x20));
myParamSetup_base = (CSL_Edma3ParamSetup *) (PARAM_BASE + (EDMA_CHANNEL_AXEVT1 * 0x20)) ; // base table, linked to the synch event
myParamSetup_ping = (CSL_Edma3ParamSetup *) (PARAM_BASE + (EDMA_CHANNEL_TX_PING * 0x20)) ; // reload ping table
myParamSetup_pong = (CSL_Edma3ParamSetup *) (PARAM_BASE + (EDMA_CHANNEL_TX_PONG * 0x20)) ; // reload pong table
// SETUP BASE TABLE
myParamSetup_base->option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN,\
EDMA_CHANNEL_AXEVT1, // TCC_CODE
CSL_EDMA3_TCC_NORMAL,\
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_DIS, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR);
myParamSetup_base->srcAddr = (Uint32)bufferTx[0];
#if DATAPORT == 0
myParamSetup_base->dstAddr = 0x4803C000 + 0x200; //MCASP1_XBUF0
myParamSetup_base->aCntbCnt = CSL_EDMA3_CNT_MAKE(8,((TDM_OUT_NUM_CH*PROC_BUFF_SAMPLE_LEN*OUT_OVER_SAMPLING)/2));
myParamSetup_base->srcDstBidx = CSL_EDMA3_BIDX_MAKE(8,0); // increment source by 4, don't increment destination
#else
myParamSetup_base->dstAddr = 0x01D06200;
myParamSetup_base->aCntbCnt = CSL_EDMA3_CNT_MAKE(4,(TDM_OUT_NUM_CH*PROC_BUFF_SAMPLE_LEN*OUT_OVER_SAMPLING));
myParamSetup_base->srcDstBidx = CSL_EDMA3_BIDX_MAKE(4,0); // increment source by 4, don't increment destination
#endif
myParamSetup_base->linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE (EDMA_CHANNEL_TX_PONG * 0x20, 1); // link table -> pong
myParamSetup_base->srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0);
myParamSetup_base->cCnt = 1;
// SETUP PING TABLE, SAME AS BASE
myParamSetup_ping->option = myParamSetup_base->option;
myParamSetup_ping->srcAddr = myParamSetup_base->srcAddr;
myParamSetup_ping->dstAddr = myParamSetup_base->dstAddr;
myParamSetup_ping->aCntbCnt = myParamSetup_base->aCntbCnt;
myParamSetup_ping->srcDstBidx = myParamSetup_base->srcDstBidx;
myParamSetup_ping->linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE (EDMA_CHANNEL_TX_PONG * 0x20, 1);
myParamSetup_ping->srcDstCidx = myParamSetup_base->srcDstCidx;
myParamSetup_ping->cCnt = myParamSetup_base->cCnt;
// SETUP PONG TABLE, SAME AS BASE BUT DIFFERENT SOURCE ADDRESS
myParamSetup_pong->option = myParamSetup_base->option;
myParamSetup_pong->srcAddr = (Uint32)bufferTx[1];
// myParamSetup_pong->srcAddr = (Uint32)bufferRx1;
myParamSetup_pong->dstAddr = myParamSetup_base->dstAddr;
myParamSetup_pong->aCntbCnt = myParamSetup_base->aCntbCnt;
myParamSetup_pong->srcDstBidx = myParamSetup_base->srcDstBidx;
myParamSetup_pong->linkBcntrld = CSL_EDMA3_LINKBCNTRLD_MAKE (EDMA_CHANNEL_TX_PING * 0x20, 1);
myParamSetup_pong->srcDstCidx = myParamSetup_base->srcDstCidx;
myParamSetup_pong->cCnt = myParamSetup_base->cCnt;
}
void testInOutEDMA_start_edma(void)
{
// clear interrupt flag
edma3Regs->ICR = 0xffffffff; // (1 << McASP2_TX);
// enable interrupt
edma3Regs->IESR = (1 << EDMA_CHANNEL_AREVT0) | (1 << EDMA_CHANNEL_AXEVT1);
// Event Enable Set Register:
edma3Regs->EESR = (1 << EDMA_CHANNEL_AREVT0) | (1 << EDMA_CHANNEL_AXEVT1);
}
#include <xdc/runtime/Error.h>
void testInOutEDMA_isr_init(void)
{
Hwi_Params hwiParams;
Error_Block eb;
Hwi_Params_init(&hwiParams);
Error_init(&eb);
/******************/
/* EDMA INTERRUPT */
/******************/ // set the argument you want passed to your ISR function
hwiParams.arg = 0;
// set the event id of the peripheral assigned to this interrupt
hwiParams.eventId = 20; // EDMAINT region 1
// don't allow this interrupt to nest itself
hwiParams.maskSetting = Hwi_MaskingOption_NONE;
Hwi_create(8, testInOutEDMA_edma_isr, &hwiParams, &eb);
if (Error_check(&eb)) {
BIOS_exit(0);
}
/*******************/
/* MCASP INTERRUPT */
/*******************/
// set the event id of the peripheral assigned to this interrupt
// hwiParams.eventId = 72; // MCATXINT1
hwiParams.eventId = 71; // MCARXINT0
// don't allow this interrupt to ...
hwiParams.maskSetting = Hwi_MaskingOption_ALL;
Hwi_create(4, testInOutEDMA_mcAsp_isr, &hwiParams, &eb);
if (Error_check(&eb)) {
BIOS_exit(0);
}
}
I have tried the two new address, but without success.
I have attached a source file.
If compiled with #define DATAPORT 0 it works fine.
I compiled with #define DATAPORT 1 it doesn't work.
If you need more information do not hesitate to ask.
I remember you that the MCASP under observation is the MCASP1 (TX side).
Thanks a lot.
Paolo.
Hi Paolo,
I received feedback that the DM814x McASP1 DAT port XBUF0 register address is 0x4640_0000. As DM814x and DM816x are very similar, can you try with that address also.
Best Regards,
Pavel