Hi,
I'm currently undertaking a project whereby I will be making a small PCB to interface a composite video camera to the DM8168 evaluation module board for the purposes of doing some DSP later on.
I'm using the TVP5147 decoder as the basis for the ADC board design, which takes the camera input through a BNC socket and outputs digital video to the EVM through high speed header(s) (QTH-xxx-01-x-D-xx), but am having some difficulty in confirming exactly which output pins from the TVP5147 need to be connected to which input pins on the EVM in order to capture 16-bit YCbCr 4:2:2 video with separate syncs on it.
So far I have established the following connections
TVP5147 | DM8168EVM |
HS/CS | VIN[0]A_HSYNC |
VS/VBLK | VIN[0]A_VSYNC |
DATACLK | VIN[0]A_CLK |
GLCO/I2CA | Pulled down to DGND |
AVID | VIN[0]A_DE |
FID | VIN[0]A_FLD |
in addition to connecting the video input bus, but remain confused about the INTREQ output pin from the decoder - does this generate interrupts which will need to be serviced by the ARM cortex for video capture to work properly? If so, which input pin on the EVM should it be connected to?
As the I2C pins on the EVM are connected to a separate header from the video inputs, I am planning to breakout the SDA and SCL signals separately and crudely wire them to my board in order for the TVP5147 to be addressed as a slave and have its registers manipulated. However, according to the EVM schematic, some of the video input sync signals corresponding to the VIN[0]A_D bus are also connected to a separate header than the bus itself, which seems rather inconvenient. Is there a workaround for this or will I have to introduce a third HS header terminal into my design (one for video out, one for I2C breakout, one for sync signals)?
Would be extremely grateful for any advice you have on the matter!
Regards
Marc