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FLDSTAT question

Anonymous
Anonymous

Hi All,

I would like to ask a question on VPFE.

VPFE.SYN_MODE has bit 15 as field identification (SPRU977a, 643x VPFE User's Guide), which I have found its description somehow strange:

Because normally,

  1. field 0 is called even
  2. field 1 is called odd

 

Why here it seems to be opposite? Is it a typo?



Sincerely,
Zheng

  • 0
    TI__Genius 14405 points

    Our designer looked into this and said the bit field basically reflects the value on the FLD signal.

    I think the description depends on how you number the field. Basically, 0 = the first field in the frame; 1= the 2nd field in the frame in both places you find contradicting.

  • Anonymous
    0 Anonymous in reply to Paul.Yin

    Dear Paul,

    Great, thanks very much for this confirmation, this clarified the confusion.

    I have still another question:

    According to p.140, SPRU977a, 643x VPFE User's Guide:

     

    Therefore, when either VDINT0 or VDINT1 is triggered, at least the time corresponding to one line of pixels has already elapsed after VD's rising edge (for NTSC: 1 (second) / 30 (whole frames) / 525 (lines)). For a DSP of 600 MHz clock rate, this corresponds to approximately 0.6M clock cycles. I figure that it is almost definitely enough for FLDSTAT bit field to be updated to reflect the status of the current field that is being read, so when VDINT0/1 ISR is reading the FLDSTAT it will also get the correct identification value of the current field.

    This is somehow a paranoid's question: do we have this guaranteed? Is it possible that there is a very very long delay (more than 0.6M clock cycles, > 1 line's time) between VD's rising edge and the update of the latest field number to FLDSTAT, so that if VDINT0/1 ISR reads FLDSTAT at its beginning (code line), FLDSTAT still haven't got updated and ISR gets the FLDSTAT value of the last field, and then we get the wrong field number?

     

    Zheng