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How to know the completion of a EDMA transfer?

gatorade
Prodigy 140 points

I do not use the EDMA3 driver interface and I write code below:

I use the 3 channels of EDMA simutaneously 

1. set  TCINTEN bit in OPT param to 1 of 3 channels

2.shadowRegs->IESR = 0x7; 

3. shadowRegs->ESR = 0x7;  // start the transfer

4....................

5.while ( shadowRegs->IPR & 0x7 != 7 );   //wait for complete

6. other process code

Unfortunitly the step 5 can not valid ,that means it do not wait for the completion of transfer in step 5.

Is there any thing wrong with my code? and How to know the completion of a EDMA transfer?

Thank you !

  • Prodigy 140 points

    Is there some one help me?

  • TI__Mastermind 41665 points

    So to understand this better, are you saying that your polling on the IPR is not valid because it ends up being set before you believe the transfer has completed or that it is never set?

    If the IPR is being set and it it looks like the EDMA has not actually completed than it could be either that you are running into a cache coherency issue if you are using external memory, or that the transfer has not physically completed yet (though it has been submitted to the transfer controller).

    If this is the first case of a cache issue than you need to make sure that you perform a writeback on the area that you are transferring from if it is CPU generated data, and a invalidate at some point before you try to read it to ensure that the data you read is what is really in external memory. This is a common issue when using bus mastering peripherals like the EDMA since they are not aware of the CPU cache. Assuming a DSP based device (DM6437) running BIOS you could do this with the BCACHE APIs discussed in the DSP/BIOS API Guide SPRU403.

    If it is the second issue than you may simply have to wait a few cycles before accessing the last bytes of data. The way the EDMA controller is designed there is no way of knowing exactly when a transfer has actually completed, you can only know when the transfer request (TR) was submitted to the transfer controller (TC), the time for the transfer controller to handle it can vary based on system load, but will usually be very soon after you get the TCC. Typically this is not an issue for larger transfers particularly if you are accessing the earlier data in the transfer first because a larger transfer will typically be several actual TC submissions (discussed in section 2.5 of the EDMA manual SPRU987, particularly table 2-6) so the earlier ones will have completed even if the last submitted TR has just triggered your TCC. 

    If the IPR is never being set, than there may be something else wrong with your EDMA configuration which could be any number of issues, if this is the case you may want to post more of your EDMA register and PaRAM configuration. 

  • in reply to Bernie Thompson TI
    Expert 2995 points

    set on beginning

    IRC=7; // Interrupt Clear Registers