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Can AM1808 upp frequency run at 48MHz (DDR mode)?It works well on my board.

yanbin xing
Prodigy 170 points
Other Parts Discussed in Thread: AM1808

I use two channels upp and one hi-speed USB device port at the same time and It works well on my board.

But the upp frequency is 48MHz (ddr mode), higher than recommened 37.5MHz (ddr mode).

 

The core frequency is 384MHz.

upp-ch-a : output 16bit * 48MHz * 2 (ddr mode) from 128KB sram

upp-ch-b : input 16bit * 24MHz *2 (ddr mode)

USB: send data to a PC HOST, the data rate is about 25~30MB/s.

 

So, is 48MHz ok? It works well whatever.

  • 0
    TI__Expert 8890 points

    Yanbin,

    TI has not tested the uPP peripheral at speeds higher than 75 MHz (SDR) or 37.5 MHz (DDR), so we don't recommend or support that use case.  That said, it is straightforward to configure the peripheral at higher speeds for devices with CPU frequency higher than 300 MHz.  You are operating in uncharted territory, so caution is advised.

    My official recommendation is to reduce your uPP clock speed to 37.5 MHz using the optional "2xTxClk" pin.  This lets you reach specific uPP clock speeds that are not achievable using integer division of the CPU clock (i.e. dividing 384 down to 75 or 37.5).

    Hope this helps.

  • 0 in reply to Joe Coombs
    Prodigy 170 points

    I need upp run at 48MHz actually.

    I will test it carefully.

    Do you have any good suggestion about testing?

  • 0 in reply to yanbin xing
    TI__Expert 8890 points

    Yanbin,

    If possible, I recommend testing this by connecting uPP to itself.  You could either do this via external loopback connections (i.e. connect Channel A and B pins together on the same device) or by connecting two boards together (i.e. Channel A to Channel A).  Once you have this connection setup, you can run tests at your desired speed.  I would suggest running many (100+) uPP transfers chained together to make sure the peripheral operates reliably at this speed.  You could even simulate system loading by setting some system EDMA transfers to run in the background (i.e. copying data buffers from external RAM to another location in external RAM).  This is the sort of testing we originally performed for uPP at 75 MHz (37.5 MHZ DDR).

    Hope this helps.

  • 0 in reply to Joe Coombs
    Prodigy 160 points

    Hi All,

    I am working on UPP driver in linux kernel. I am trying to test the LOOP BACK for the UPP for AM1808 board. I have configured CH-A as TX and CH-B as RX. I am always getting data as a zero. Could you please let me know any configuration is missing.

    Could you please share the source code for UPP driver in linux kernel.

    How do I tap data and clk signals on upp data pins?

    Thanks,

    Mrudula

  • 0 in reply to mrudula chougule
    TI__Guru** 116100 points

    Hi Mrudula,

    I have seen your replies to old uPP threads.

    Can you please create a new thread for this issue as posting on the same thread will get only less attention when compared to the new one.