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SPI1 only about 2MHz clock rate?

Paul Singh
Expert 2750 points
Hi,
 
I see a disparity between SPI1 FLASH speed:

1.    When I am using the evmomapl138 SPI flash driver to written AISgen result into FLASH, I used scope and see that the frequency is only ~150KHz.

2.    However when booting from SPI1 FLASH, the frequency scope see is ~2.4MHz.

·         Even this ~2.4MHz speed is far slower than the 30MHz SPI1 speed I actually specified in AISgen


What has caused this huge difference?

 
The SPIFMTn register of SPI module (Table 30-26 of SPRUH77):
Table 30-26 of SPRUH77 said:
It determines the bit transfer rate if the SPI is the network master and is directly derived from the SPI module clock. If the SPI is configured as slave, PRESCALE needs to be configured to a valid value, but PRESCALE is ignored.
The clock rate can be calculated as:
SPI clock frequency = SPI module clock/(PRESCALE + 1)
According to <Table 7-2. System Clock Domains, SPRUH77>, SPI1 uses ASYNC3, and I set
 

1.    CFGCHIP3. ASYNC3_CLKSRC = 0

 
so that PLL0_SYSCLK2 = CPU clock/2 = 150MHz is used. I have also checked PLL0. PLLDIV2 at address 0x01c1111c and its value is 0x00008001, which means it is enabled and divide ratio is 1+1=2, confirming that the clock source for SPI1 is indeed PLL0_SYSCLK2 = 150MHz.
For SPI1 there is SPIFMT0-3 and which one is used is controlled by SPIDAT1.DFSEL. I simply set

 

1.    SPIFMT0 = SPIFMT1 = SPIFMT2 = SPIFMT3 = 00010208,

2.    And tried setting SPIDAT1.DFSEL to all 0, 1, 2 ,3 values and test

o    In this situation whatever value DFSEL is, the clock rate should be = 150 MHz / (2+1) = 50 MHz

 
 
However, what I do observe when executing SPI_xfer() of evmomapl138_spi.c is that the clock as seen by the scope can never get larger than 2.4MHz. Sometimes if I change SPIFMT1(0, 1, 2, 3) values then the scope might see some difference, can be as low as 130KHz and as high as 2.4MHz, but never any higher.
     
Could someone help to look at the problem? I cannot image why although SPI module clock/(PRESCALE + 1)  = 50MHz, I only get ~1MHz SPI1 clock? I have tried to use other PRESCALE values and only got worse, such as down to 300KHz, and have never seen anything close to the expected 50MHz value; in addition, as described at the beginning, from AISgen booting I also see a much lower speed (2.4MHz) than specified (50MHz). Where is the problem?
 
 
Paul
  • 0
    TI__Guru** 116170 points

    Paul,

    I can explain the numbers during booting the AISGen image but might need more information about the user level code. If you look at chapter nine of bootloader application notes(Boot requirements,constriants and restrictions) that explains the default freq/prescalar values used by the ROM bootloader, that might explain ~1Mhz, you are seeing.

    Are the drivers you are using, obtained from the serial flash and boot utilities ?

    Regards,

    Rahul

  • 0 in reply to Rahul Prabhu
    Expert 2750 points

    Rahul,

    Thanks for the answer. I looked at <Table 6. Default Clock Configurations for Various Boot Modes (continued)> of the note and see when L138 serves as SPI master with 24MHz clock the clock rate is 800KHz, so that might be close to what I am experiencing (~2MHz), and it seems that the SPI1 clocking configuration in AISgen is not applicable to this?

    Durning normal running of the code, I did quite extensive testing and found that the low speed is due to memory hierarchy access. The data that I am writing to FLASH is placed in DDR2 and the naive driver of EVMOMAPL138 needs to retrieve each byte in a for-loop which drastically slowed down the speed; I did a test which places all code into 128KB L2 memory and write some arbitrary pattern (like 0xAABBCCDD, etc.) repeatedly into SPI.SPIDAT1 register, and in this case there is virtually no memory access delay. I could see SPI clock raised to ~24MHz although when actual PLL0_SYSCLK2 is 150MHz and PRESCALE = 2. 

    I also tried replace the byte-by-byte memory access with EDMA, and the speed has been increased to ~2MHz during normal operation. It is slower than the maxiumu 50MHz because the Flash driver has its own program logic and many internal calculation and FLASH status check, necessary waits, etc., cannot all be implemented with EDMA. Nevertheless, this is already over 10 times faster than the original byte-by-byte access and is enough for our use.

    Paul

  • 0 in reply to Rahul Prabhu
    Expert 2750 points

    Rahul,

    Could you also have a look at Cannot set EDMA3’s IER registers even when DRAEn enabled?

    Being able to use EDMA3 interrupt is crucial to our use case, and I have already been trying different methods on this for hours without seeing any change, really frustrated.

    Paul