• State Resolved
  • Locked Locked
  • Replies 8 replies
  • Subscribers 98 subscribers
  • Views 788 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Using the C6746 UHPI_HAS pin

Daisuke Maeda
Guru 20205 points
Other Parts Discussed in Thread: TMS320C6746, AM3359

C6746 TRM (SPRUH80A) describes that UHPI_HAS pin is connected to logic high.
I guess that UHPI_HAS pin must be not used except used as GPIO.

C6746 datasheet (SPRS591C) describes the Timing Requirements for UHPI_HAS pin.
Why are there the Timing Requirements?

Best regards,

Daisuke

 

  • 0
    TI__Expert 7470 points

    Hi,

    The timing parameters are provided for the case where the HAS signal IS used (these particular parameters are present only in diagrams that specifically mention: "HAS USED". This supports a special case where the host processors has a limitation to multiplex address and data on the same bus.

    In most cases (where host is an MPU), the HAS signal is not relevant as the interface can be programmed as needed. Hope this clarifies the issue for you.

    Regards,

    Sunil Kamath

     

  • 0 in reply to Sunil Kamath
    Guru 20205 points

    Hi Sunil,

    Thank you for your reply.

    TRM does not detail "HAS USED".
    TRM describes only that UHPI_HAS pin is connected to logic high.

    Is "HAS USED" supported by C674x?

    Best regards,

    Daisuke

     

  • 0 in reply to Sunil Kamath
    Guru 20205 points

    Hi Sunil,

    Thank you for your reply.

    If C674x supports "HAS USED", why are not there the details in TRM (SPRUH80A)?

    Best regards,

    Daisuke

     

  • 0 in reply to Daisuke Maeda
    TI__Expert 7470 points

    Hi Daisuke,

    Some further clarification - as you must have observed from the documentation the UHPI on OMAP-L13x, C674x device only supports multiplexed host address/data mode with the help of the HPIAR/W address registers. This can be achieved with and without the use of UHPI_HAS pin.

    The need to use the UHPI_HAS signal would arise only when the host is not able to meet the timing requirements for signals (such as UHPI_HCNTL[1:0], UHPI_HR/W, etc.) with respect to the internal HSTROBE signal which is a logical operation of other signals provided by the host (UHPI_HCS, UHPI_HDS1, and UHPI_HDS2).

    So essentially the the only difference (operation-wise) between the two use cases is how the host meets the timing requirements of the UHPI. This does not seem to be well communicated in the TRM.

    Hope this clarifies your question.

    Regards,

    Sunil Kamath

  • 0 in reply to Sunil Kamath
    Guru 20205 points

    Hi Sunil,

    Thank you for your reply.

    It was clarified that the C674x supports "HAS USED".

    Best regards,

    Daisuke

     

  • 0 in reply to Sunil Kamath
    Guru 20205 points

    Hi Sunil,

    "For correct operation, strobe the UHPI_HAS signal only once per UHPI_HSTROBE active cycle."

    This is described in C6746 datasheet.

    Does the UHPI_HSTROBE active cycle mean a period when UHPI_HCS is Low?

    TMS320C6746 Fixed- and Floating-Point DSP (Rev. D)
    http://www.ti.com/lit/ds/sprs591d/sprs591d.pdf
    Figure 5-54. UHPI Read Timing (HAS Used)
    Figure 5-56. UHPI Write Timing (HAS Used)

    Our customer uses C6746 with AM3359. UHPI_HAS connects to GPMC_ADVn_ALE. GPMC_ADVn_ALE during inactive cycle is Low.
    The write access after the read access fails then some data buses show the voltages between the high level and low level.

    Sitara AM335x ARM Cortex-A8 Microprocessors (MPUs) (Rev. F)
    http://www.ti.com/lit/ds/sprs717f/sprs717f.pdf
    Figure 5-26. GPMC and Multiplexed NOR Flash - Asynchronous Read - Single Word
    Figure 5-27. GPMC and Multiplexed NOR Flash - Asynchronous Write - Single Word

    When GPMC_ADVn_ALE configured as a GPIO pin is used, GPMC_ADVn_ALE during inactive cycle is High. The write access never fails.

    Best regards,

    Daisuke

     

  • 0 in reply to Sunil Kamath
    Guru 20205 points

    Hi Sunil,

    For correct operation, is not it allowed for UHPI_HAS to be Low in a period when UHPI_HCS and UHPI_HDS1 and UHPI_HDS2 are High?

    Best regards,

    Daisuke