EDMA to SPI - No Activity

Ahh yes setting up DMAREQEN as well, I did set that before it started working.  Its just been several hours since I enabled that so I forgot.  You will need to kick start the DMA as well.

Well I now have constant activity on the SPI line but it doesn't appear that the EDMA is actually transfering anything.  Only zeros are sent on the SPI line (the chip select and clock look good).  And my input buffer is not overwritten with zeros like it should be (spi in is floating).  I am pretty confident that I am writing and reading to the proper memory locations for the SPI as I can manually write to them and get the desired results.  I have the following code:

#include <stdio.h>
#include <ti/pspiom/cslr/soc_OMAPL137.h>
#include <ti/pspiom/cslr/cslr_spi.h>

#define SPI_NUM_OF_TXBITS        16
#define SPI_NEW_DATA_NO            0x01

CSL_SpiRegsOvly  spiRegs=(CSL_SpiRegsOvly)CSL_SPI_0_REGS;

static void Spi_dev_init();
static void Spi_test();
static Uint16 txlist[4];
static Uint8 rxbuf[4];
static Uint8 test[4];

void main(void)
{
    /* now initialise the SPI controller with appropriate settings            */
    Spi_dev_init();

    /* test the SPI interface by sending the data                             */
    Spi_test();
}

static void Spi_dev_init(void)
{
    /* First reset the SPI chip                                               */
    spiRegs->SPIGCR0 = CSL_FMK(SPI_SPIGCR0_RESET, CSL_SPI_SPIGCR0_RESET_IN_RESET);

    /* now bring the chip out of reset state                                  */
    spiRegs->SPIGCR0 = CSL_FMK(SPI_SPIGCR0_RESET, CSL_SPI_SPIGCR0_RESET_OUT_OF_RESET);

    /* enable the CLKMOD and MASTER bits in the SPI global control reg        */
    spiRegs->SPIGCR1 |=  CSL_FMK( SPI_SPIGCR1_MASTER,0x01)
                     | CSL_FMK(SPI_SPIGCR1_CLKMOD,0x01);

     /* enable the pins so that they are used for the SPI interface(Multiplex) */
    spiRegs->SPIPC0  = CSL_FMK(SPI_SPIPC0_CLKFUN ,0x01)
                     | CSL_FMK(SPI_SPIPC0_SOMIFUN ,0x01)
                     | CSL_FMK(SPI_SPIPC0_SIMOFUN ,0x01)
                     | CSL_FMK(SPI_SPIPC0_SCS0FUN ,0x01);

    /* configure the data format in SPIFMT                                    */
    spiRegs->SPIFMT[0] = CSL_FMK(SPI_SPIFMT_CHARLEN,SPI_NUM_OF_TXBITS)
                       | CSL_FMK(SPI_SPIFMT_PRESCALE,0x04);

    /* set the preconfigure data format as 0 which is already set above       */
    spiRegs->SPIDAT1 = CSL_FMKT(SPI_SPIDAT1_DFSEL,FORMAT0)
                     | CSL_FMK(SPI_SPIDAT1_CSNR,2);

    spiRegs->SPIGCR1 |=  CSL_FMK(SPI_SPIGCR1_ENABLE,0x01);

    spiRegs->SPIINT0 = CSL_FMKT(SPI_SPIINT0_DMAREQEN,ENABLE);

/*    set txlist */   
    txlist[0] = 0xFFFF;
    txlist[1] = 0xFFFF;
    txlist[2] = 0xFFFF;
    txlist[3] = 0xFFFF;
/*    set rxbuf */
    rxbuf[0] = 0xFF;
    rxbuf[1] = 0xFF;
    rxbuf[2] = 0xFF;
    rxbuf[3] = 0xFF;

    test[0] = 0x00;
    test[1] = 0x00;
    test[2] = 0x00;
    test[3] = 0x00;

/*    setup registers for PaRAM Set 14    */
    /* OPT */
    *( volatile Uint32* )0x01C041C0 = 0x00100000;
    /* SRC */
    *( volatile Uint32* )0x01C041C4 = 0x01C41040;
    /* A_B_CNT */
    *( volatile Uint32* )0x01C041C8 = 0x00010001;
    /* DST */
    *( volatile Uint32* )0x01C041CC = ( Uint32 )rxbuf;
    /* SRC_DST_BIDX */
    *( volatile Uint32* )0x01C041D0 = 0x00010000;
    /* LINK_BCNTRLD */
    *( volatile Uint32* )0x01C041D4 = 0x00014800;
    /* SRC_DST_CIDX */
    *( volatile Uint32* )0x01C041D8 = 0x00000000;
    /* CCNT */
    *( volatile Uint32* )0x01C041DC = 0x00000001;

/*    setup registers for PaRAM Set 64    */
    /* OPT */
    *( volatile Uint32* )0x01C04800 = 0x00100000;
    /* SRC */
    *( volatile Uint32* )0x01C04804 = 0x01C41040;
    /* A_B_CNT */
    *( volatile Uint32* )0x01C04808 = 0x00010001;
    /* DST */
    *( volatile Uint32* )0x01C0480C = ( Uint32 )rxbuf;
    /* SRC_DST_BIDX */
    *( volatile Uint32* )0x01C04810 = 0x00010000;
    /* LINK_BCNTRLD */
    *( volatile Uint32* )0x01C04814 = 0x00014800;
    /* SRC_DST_CIDX */
    *( volatile Uint32* )0x01C04818 = 0x00000000;
    /* CCNT */
    *( volatile Uint32* )0x01C0481C = 0x00000001;

/*    setup registers for PaRAM Set 15    */
    /* OPT */
    *( volatile Uint32* )0x01C041E0 = 0x00101000;
    /* SRC */
    *( volatile Uint32* )0x01C041E4 = ( Uint32 )txlist;
    /* A_B_CNT */
    *( volatile Uint32* )0x01C041E8 = 0x00010001;
    /* DST */
    *( volatile Uint32* )0x01C041EC = 0x01C41039;
    /* SRC_DST_BIDX */
    *( volatile Uint32* )0x01C041F0 = 0x00000001;
    /* LINK_BCNTRLD */
    *( volatile Uint32* )0x01C041F4 = 0x00014820;
    /* SRC_DST_CIDX */
    *( volatile Uint32* )0x01C041F8 = 0x00000000;
    /* CCNT */
    *( volatile Uint32* )0x01C041FC = 0x00000001;

/*    setup registers for PaRAM Set 65    */
    /* OPT */
    *( volatile Uint32* )0x01C04820 = 0x00101000;
    /* SRC */
    *( volatile Uint32* )0x01C04824 = ( Uint32 )txlist;
    /* A_B_CNT */
    *( volatile Uint32* )0x01C04828 = 0x00010001;
    /* DST */
    *( volatile Uint32* )0x01C0482C = 0x01C41039;
    /* SRC_DST_BIDX */
    *( volatile Uint32* )0x01C04830 = 0x00000001;
    /* LINK_BCNTRLD */
    *( volatile Uint32* )0x01C04834 = 0x00014820;
    /* SRC_DST_CIDX */
    *( volatile Uint32* )0x01C04838 = 0x00000000;
    /* CCNT */
    *( volatile Uint32* )0x01C0483C = 0x00000001;
/* EESR */
    *( volatile Uint32* )0x01C01030 = 0x8000;
}

static void Spi_test(void)
{
    Uint8 tx= 0x40; /* test string to transmit*/
    //CSL_FINS(spiRegs->SPIDAT1,SPI_SPIDAT1_TXDATA, tx);   
    while(1)
    {                     
    }
}

When I take a look at my memory everything looks well:

0x01C041C0    81100000    01C41040    00010001    008017B8    00010000    00014800    00000000    00000001
0x01C041E0    81101000    008017B0    00010001    01C41039    00000001    00014820    00000000    00000001
0x008017B0    txlist   
0x008017B0    FFFFFFFF    FFFFFFFF
0x008017B8    rxbuf   
0x008017B8    FFFFFFFF    077C5F77

Your EDMA configuration for the transmit side looks suspect to me.  In particular, why are you writing to address 0x01C41039?  The SPIDAT0 register description says, "Irrespective of the character length, the transmit data should be right-justified before writing to SPIDAT0 register."

There's also this note in that same register description that sounds similar to what you're describing:  "SPIGCR1.ENABLE must be set to 1 before this register can be written to. Writing a 0 to the SPIGCR1.ENABLE forces the TXDATA[15:0] field to 0."  Your code appears to have already set the enable, but perhaps you should double-check in the register view.

Brad

I am writing to 39 instead of 38 because I am only actually worried about the first 8 bits.  I found my problem was that I was using L2 RAM locations starting at 0080 for my input/output arrays, apparently the EDMA doesn't play nicely with these locations.  This code then started to work correctly once I switched my cmd file to use L2 RAM starting at 1180.

Ah ha!  Good one.  Yes, that makes perfect sense because the 0080xxxx address is a "local" address inside the megamodule whereas the 1180xxxx address is the global address.  That's shown inside the datasheet in the "Memory Map" section.  It shows that only the DSP can access that address range.

So I assume you needed to change your linker ocmmand file in order for this to take effect?  Were you using BIOS?  I haven't looked to see which address BIOS maps by default.

Brad