• State
  • Locked Locked
  • Replies 1 reply
  • Subscribers 97 subscribers
  • Views 346 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RESETOUT deassertion to first instruction fetch from boot device

Dinesh Balasubramaniam
Intellectual 480 points

Question about the boot sequence on the OMAP L138.

Figure 5-4 on the datasheet shows that after a POR, RESETOUT gets deasserted 6169 cycles after RESET is deasserted and the boot pins latched.  On a warm boot, this delay is 4096 cycles.  In our system we connect RESETOUT to the reset pin of the SPI flash device used for boot.  So we need to be guaranteed that no instructions will get fetched during this delay, since the flash chip would still be in reset.  

  • How does the L138 determine when to issue the first instruction fetch after RESETOUT is deasserted? 
  • What is the internal clock configured when the device first comes up?
  • How many cycles does it wait before it fetches the first instruction? 

Thanks,

Dinesh

  • 0
    TI__Guru* 83875 points

    Hi Dinesh

    Although I don't think it is explicitly stated in the documentation, RESETOUT is released as soon as the last hardware reset operation is complete.  The CPU will not begin the boot process until all reset operations have finished so you can safely assume that the boot process will not begin until RESETOUT has been released.

    Additionally I would assume that your SPI flash will not start sending any data till the RBL gets the SPI CS low etc?

    Are you seeing any issues? Have you measured the timings from RESET/RESETOUT to first SPI activity etc?

    Regards

    Mukul