C6747 timer1 interrupt

Feng Sun,

A good example for you to look at is located in the PSP package.

If you do not already have the BIOSPSP package, you can find here:
http://software-dl.ti.com/dsps/dsps_registered_sw/sdo_sb/targetcontent/psp/bios_psp/1.30.xx/1.30.00.05/BIOSPSP_01_30_00_05_Setup.exe

The example will be located following this directory structure:
\packages\ti\pspiom\cslr\evm6747\examples\timer\

Hope this helps.

-Kevin

Feng Sun,

As a side note, it appears that updating the linker command file may fix the issue.

In the main() function, ISTP is assigned to 0xFFF00000. (This corresponds to VECS in the linker command file.)

However, the section .vectors (which corresponds to _intcVectorTable in vector.asm) is assigned to SHAREDRAM and not VECS.

I would suggest modifying ".vectors > SHAREDRAM" to ".vectors > VECS" as a starting point to debug.

-Kevin

sorry for the mistake...actually .vectors was mapped into VECS before i came for help, i just type the wrong version of my link file..sorry again

but i think i have ...kind of  fixed the problem, although i don't know why it works like this .  what i have done were:

1.build the project again

2. reload

3. i found that  _c_int0 was in address 0x80003800, so i juest change my ISTP into that and rebult and reloaded, ....and it worked 

so here is some other questions come up:

1. how to set ISTP correctly, i mean not like the kind of the way i just used.

2. there are four INT pins(INT0-INT3) on C6747, how to use them as a interrupt generater?  right now i can just use them as a common GPIO pin

byt, it is such a big surprise to see u reply to my post so quick...thanks a lot for what u have said and the time u have spent

THANKS a lot!

i am now using CCS Ver.3.3. 

about the INT pins, maybe i was a little bit confused because the development kit we bought (DEC6747 by SEED) use four of GPIO pins as INT0-INT4.

Feng Sun,

Glad to see everything is working now!

If you don't mind, please mark the post which was the most beneficial as "Verified Answer" to notify others that this forum thread contains a solution.

about the INT pins, maybe i was a little bit confused because the development kit we bought (DEC6747 by SEED) use four of GPIO pins as INT0-INT4.
If there is still confusion, let me know and I will see if I can better understand the problem. The context (source code) may be beneficial.

Thanks,
Kevin

Thanks i tried that and it worked.

Now i am moving on to let the C6747 to read frames of data from an outside FIFO built in a FPGA or sth.

The data is read from EMIFA using EDMA, every reading process is triggered by a rising edge of GPIO2[4]

The problem here is that when a rising edge is provided on the GPIO2[4] pin, the GPIO interrupt is triggered and corresponding function is executed, but the EDMA refuses to work. 

Then i tried to run in CCS step by step, and i found that when

void set_EMIFA(){
......

    AEMIF_A4CR |= 0 << 31 |                  //set Asyncronise clocks  in CE4CEG
                  1 << 30 |
                  (1 & 0xFF) << 13 |
                  (3 & 0x0F) <<  7 |
                  (2 & 0x0F) <<  4 |
                  (0 & 0x0F) <<  0;

......
}

is executed, nothing happened on the register CE4CFG, and it remained 0.

followed is my main.c

#define FIFO_ADDR      0x67000000
#define BUFF_ADDR    0x80000000
#define INTMUX1            *( volatile Uint32* )(0x01800104)
#define FIFO_DEPTH    256
#define NUM_FRAMES 8

#include<C6747.h>
#include<c6x.h>
#include<stdio.h>
 
int num_frames = NUM_FRAMES;
int done = 0;

void set_EDMA();
void set_intr();
void set_EMIFA();
void set_GPIO();
interrupt void c_int04();
interrupt void c_int05();

void main(){ 
    ISTP = (unsigned int)vectors;
    C6747_init();
    CSR &= ~0x01;   // intrrupt gloabe disabel
    set_GPIO();
    set_EMIFA();
    set_EDMA();
    set_intr();
    while (!done);
    printf("DONE \n\n");
    EDMA_ICR |= 0x01;
}
void set_GPIO(){                                             // Set GPIO2[4] to be HF in pin
     GPIO_DIR23 |= 0x1<<4;                          // direct: input
     GPIO_BINTEN &= ~0xFF;          
     GPIO_BINTEN |= 0x1<<2;                       // enable GPIO band2 interrupt
     GPIO_SET_RIS_TRIG23 |= 0x1<<4;    // enable rising edge interrupt
     GPIO_CLR_FAL_TRIG23 |= 0x1<<4;   // disable falling eged interrpt
}
void set_EDMA(){
           /*EDMA initialization */
              SAOPT0 = 0x00100071;                   // lowest priority
              QWMTHRA =(16<<8u)|(16 & 0xFF);
              EMCR =  0xFFFFFFFF;                     // clear previous missed events
              CCERRCLR = 0xFFFFFFFF;           // Clear previous errs
  
         /* Programming DMA Channel (and Param set) */
             DMAQNUM0=0x0;                              // Event is queued in queue 0
             CH0_OPT = 0x00100000;             

             CH0_SRC = FIFO_ADDR;
             CH0_A_B_CNT = ((1 << 16u) | ((FIFO_DEPTH / 2) & 0xFFFFu));    /* ACNT = 128, BCNT = 1 */
             CH0_DST = BUFF_ADDR;
             CH0_SRC_DST_BIDX = (0 << 16u) | ((FIFO_DEPTH / 2) & 0xFFFFu);    /* SRC_BIDX = 0, DST_BIDX = 128 */
             CH0_LINK_BCNTRLD = (1 << 16u) | 0xFFFFu;    /* LINK = 0xFFFF, BCNTRLD = 1 */
             CH0_SRC_DST_CIDX = 0;
             CH0_CCNT = 1;
             EDMA_ISER |= 0x01; //enable channel0 complete interrupt
}
void set_EMIFA(){
       KICK0R = 0x83e70b13;
       KICK1R = 0x95A4F1E0;    
       PINMUX18 = 0x11100012;  // EMA_WE_DQM[1-0],EMA_WE,EMA_OE,EMA_CS[5]
       KICK0R = 0;                // Kick0 register + data (unlock)
       KICK1R = 0;                // Kick1 register + data (unlock)
       AEMIF_A4CR = 0;
       AEMIF_A4CR |=  0 << 31 |                  //set Asyncronise clocks
                                      1 << 30 |
                     (1 & 0xFF) << 13 |
                      (3 & 0x0F) <<  7 |
                      (2 & 0x0F) <<  4 |
                       (0 & 0x0F) <<  0;
}

void set_intr(){
                  INTMUX1 &= ~0xFFFF;                   // clear out INTSEL4 INTSEL5 field
                  INTMUX1 |= 49 |(50<<8);                // INTSEL4=49(GPIO BANDK2), INTSEL5=50(EDMACC0)
                  IER |= 0x00000033;                          // IE4=1, IE5=1
                  CSR |= 0x00000001;                       // intrrupt gloabe enabel
}

interrupt void c_int05(){  /* DMA complete Interrupt */
              num_frames--;/* Decrement frame counter */
              printf(" one frame has been transmitted\n");
              EDMA_ICR |= 0x01;
              if (num_frames > 0)
                      IER |= 0x01<<4;    /* enable GPIO bank2 interrupt, to detect the next rising edge of HF */
              else
                     done = 1;
}

interrupt void c_int04() {
                 IER &= ~(0x01<<4);  //disable GPIO bank2 interrupt
                                                            /* so that any toggling of the HF flag is disregarded until the DMA*/
                                                            /* transfer is complete.         */
                 if (num_frames > 0)
                      EDMA_ESR |= 0x1;    /* Starts the DMA transfer, if haven’t transferred the desired number of frames.  */
                 printf("a new frame is started\n");
}