OMAP 3530 gpmc driver

I can help you with some of the basic things,

The GPMC configuration currently happening through u-boot(2010.06)/x-loader only, Kernel (2.6.32) only reads the configuration done by u-boot and uses it to find mapped/configured physical address and maps it to kernel virtual.

Based on your requirement, whether you want to transfer it one time or you need user space interface for transfer you have to write simple driver (could be simple char driver) for data transfer over GPMC to FPGA.

You have to come up with GPMC configuration based on FPGA interface, please refer to the existing NOR/NAND/ONENAND GPMC configuration setting in u-boot ("arch/arm/cpu/arm_cortexa8/omap3/mem.c" and function  "gpmc_init").

Hope above information would give you some basic idea and direction.

Thanks,

Vaibhav

Hello Michael,

to add to Vaibhav's post, here is a wiki article on GPMC setup.

http://processors.wiki.ti.com/index.php/Tips_for_configuring_OMAP35x_and_AM-DM37x_GPMC_registers

Hi:jeff

thank you very much for your help!

what is means " NOR/NAND/ONENAND GPMC" . do you know how to set up wait signal as interrupt signal?

do you know where I can find gpmc interface FPGA code which will work with OMAP interface?

Sincerely,

Michael

Hello Michael,

those are just some of the devices that interface to our General Purpose Memory Controller (GPMC).  The setup for the GPMC will have to be determined by the requirements for the particular FPGA you are using.  For determining the proper setup you will need to use the Technical Reference Manual (TRM) secrtion 11.1.  You can get the TRM from the product folder page (www.ti.com/omap3530). 

Hello,

I'm trying to access FPGA registers as if the device was a small, non-multiplexed static RAM device (size<=2048 bytes). I did it by registering a platform device driver. For now, the driver is manually loaded (for testing/debugging convenience). Linux registers the device on CS3* with success and it shows up in /proc:

root@am3517-evm:/run# cat /proc/iomem

00000000-00000000 : omap2-nand.0

01000000-01000400 : FPGA_REG.1

  01000000-010003ff : CBA_FPGA_Reg

30000000-30000003 : omap2-nand

However, when I try to acess it (from kernel space), I get a segmentation fault error and, if I try to unload the module, the kernel replies that it is in use. The only solution at that point is to reboot Linux: I probed with a scope during FPGA access and I didn't see any activity on CS* (always high) and clock (always low). 

[  327.571441] read FPGA at base address:d0898000

[  327.579864] Unhandled fault: external abort on non-linefetch (0x1008) at 0xd0898000

[  327.587982] Internal error: : 1008 [#1]

[  327.591979] last sysfs file: /sys/devices/virtual/net/lo/flags

[  327.598114] Modules linked in: FpgaGpmcDriver(+)

hi,Michael,have you solve this problem,I am also feel configure about this problem,I am looking forward to your reply.my email address is arlene0606@gmail.com.

Yes, I finally made it: Linux kernel can 'talk' to an FPGA as if it was a memory device. The FPGA emulates a synchronous RAM memory. Address/data buses are not multiplexed for the sake of symplicity. The GPMC controller allocates a small, 4 kb address space for it but that's not an issue for my application: the FPGA is programmed to 'show' less than 256 registers on its GPMC interface.

So, in retrospective, here is a list of things to keep in mind:

- I implemented the FPGA device driver as a platform device driver. I chose ioctl() function calls to let user application access the FPGA;

- Timing  specifications must be set in nanoseconds in the gpmc_timings structure, not gpmc_clocks ticks, as I originally assumed they were;

- compiling the kernel gpmc driver in debug mode helps tracing down incorrect timings: it's easy to specify timing values which exceed the range of their respective bit maps in GPMC config registers;

- At first, make sure the kernel does not turn off unused clocks (it's a kernel config option).

- Make sure that the gpmc_clock pad is set as input/output: the GPMC hardware monitors it to tweak its timing.

- keep it simple: use simple memory interface signals (ex: static RAM cs*, rd*, wr* signals) and relaxed timings: for example, my read/write cycles take about 200ns to complete and I use a 100MHz gpmc_clock.

- don't be afraid to 'hack' the kernel: need to call hidden (static) kernel GPMC functions? Just export() them. I had to do so in order to do extra configuration works on the GPMC-FPGA intervace.

It all works for me now. That required lots of head scratching, experimentation and probing but accessing the FPGA is a breeze now.

Good Luck!

hi,Yves,I am really a new starter of linux kernel,I even can't find gpmc_timings structure,I am not sure about the kernel version of mine is the same as yours.I also can't find the configuration of the gpmc register and the definition of gpmc register,such as GPMC_CONFIG1_i(i=0..7).I really need your source code,even a demo,I can read and understand the code,but the concept or datasheet may not work for me,the time left is short for my work. By the way,happy new year!Thanks a lot!

Thanks, best whishes for the Year of the Dragon too...

Time is the essence indeed... It took me about six months to get confortable with kernel hacking and documentation about GPMC drivers was sparse. We called in external help to get it working. The code is a bit too large for direct posting here so I must find another way to 'show it off'. It is also very project-specific and I'd like to review it before publishing. 

Here are two additional pointers:

The kernel source file path for GPMC function is (in my package ): ~/arch/arm/mach-omap2/gpmc.c

The kernel header file path (for th gpmc_timing_t structure): ~/arch/arm/plat-omap/include/plat/gpmc.h

Happy coding!

Hi Yves,

I'm new to Linux and is also exploring the use of GPMC with a FPGA acting like a memory device. Read/Write to register/address.

Can you zip up your driver's source code and related user-land test application to a sharing site such as yousendit for us as a good reference model?

Many thanks in adv.

James.

Hello James,

I'm currently rushing to meet software release deadline  but I'll be glad to share the code as soon as I can. I think I can do that within a few weeks from today's date.

This website probably has code sharing sections as well: as a matter of fact, I could easily attach a tar.gz file to the next post, when I'll be ready to publish.

good luck,

Yves

Hi Yves,

Thank you so much for agreeing to share the code.

I look forward to learning from your contribution.

My setup is similar to yours.

A OMAP3530 (Overo) connected to the Xilinx FPGA via the GPMC bus to read/write to registers in the FPGA in synchronous, non-multiplexing mode.

Reading your post,

"Timing  specifications must be set in nanoseconds in the gpmc_timings structure, not gpmc_clocks ticks, as I originally assumed they were;"

I look at the TRM and they are to be calculated in terms of clks. The GPMC bus is shared with a SMSC911X Ethernet chip and the frequency is 83MHz.

Can you explain a bit of the above?

Many thanks in adv.

James

thanks a lot,how did you know I am a chinese?春节快乐！I  am looking forward to your code release.during the waiting timing,I have another FPGA to deal with.ASAP please!

Hi Yves,

While you are reviewing and scrubbing the code for sharing, can you advise on the CONFIGi configuration that you used?

I want to configure OMAP3530 to FPGA using non-multiplexed, synchronous, single access RW mode.

1) I found that the L3 clock is 166MHz and the GPMC clock is limited to 83MHz in this case. TRM stated that the maximum is 100MHz (when L3_clk divide by 1), thus it seems GPMC clock is limited to 166MHz divided by 2 giving 83MHz maximum.

Can you advise if your L3 is 100MHz or 166MHz and the GPMC clock output?

I got that by dropping this code in arch/arm/mach-omap2/gpmc.c - gpmc_init()

        rate = clk_get_rate(gpmc_l3_clk);
        printk(KERN_ALERT "gpmc_l3_clk frequency: %lu", rate);

2) TRM Chap 11.1.3.3 & 11.1.3.3.1 mentioned that non-multiplexed device is supported with an address range of only 2 Kbytes.
And, there is a GPMC.GPMC_CONFIG[1].LIMITEDADDRESS bit to be set to 1 in such case.

I'm just getting started into Kernel hacking - and have a need to do something similar. The FPGA interface can be anything required at this point. I want to use the BeagleBone as the development platform for this.  Has the driver described in this sequence been made public yet?  This sound about exactly what I'm in need of.  This would be a GREAT thing to make part of the BeagleBone generic I/O offerings since the GPMC makes it up to the 80 I/Os available on the board.

HI Steven,

            i have the same requriments for the beaglebone. did you get any answer for the post?

Regards,

Dhiraj

Are there any answer to Steven's request?

I haven't received a direct answer to the question.  I ran into Jason Kridner of TI this last weekend at the Maker Faire in San Mateo, CA this weekend and spoke to him about it.  He indicated that the current Angstrom release can be configured by setting the correct values in /sys/fs to set up the Muxing from User space.  This leaves the problems of configuring the GPMC & accessing the GPMC from userspace to be resolved.  I think you can use mmap to map the GPMC into Userspace - that's the theory. Haven't had a chance in the last few days to try things out though.

Steve

Thank you for the response. can you point me to document or website where i can get more information or refrences for the correct values and the files in /sys/fs that are needed to be modified.

I really apprecate you help on the topic.

Dhiraj

hi,Yves

since you have not published the code here,I do the single read and write well.but I met a problem when I do the sync burst read:

I listened to your advice,export the function gpmc_cs_set_timings ,and add some code like below to do the sync burst read:

l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
    l=l|GPMC_CONFIG1_READTYPE_SYNC;
    l=l|GPMC_CONFIG1_READMULTIPLE_SUPP;
    l=l|GPMC_CONFIG1_CLKACTIVATIONTIME(1);
    gpmc_cs_write_reg(cs, GPMC_CS_CONFIG6, 0x0);

I call this function in my driver code,print the register,the result is look like below,I only want to do sync burst read,but I can't read anything on the D[0]-D[15] lines

I am looking forward to your reply.please help me,if you can give me some source code about sync burst read,It would be better for me to understand.Thanks again.

GPMC_CS_CONFIG1=62001001
GPMC_CS_CONFIG2=001c0b00
GPMC_CS_CONFIG3=00010900
GPMC_CS_CONFIG4=16090b00
GPMC_CS_CONFIG5=02091e0b
GPMC_CS_CONFIG6=00000000
GPMC_CS_CONFIG7=00000f6c

vjQ92K

Hi Zou,

            I am working on a similar kind of project where i need to read from  a FPGA  using GPMC. I want to know if you used a existing driver or you wrote the driver for the device?. if you wrote the driver can you provide me with the steps to follow to produce the device driver for GPMC.

Thank you .

Regards,

Dhiraj Jadhav

hi Dhiraj,

I wrote it myself,haven't achieve the sync burst,only do the single read/write well.I am so sorry I can't give the source code to u,cause it belongs to my company.Here is a helpful link for u,hope it can help u.

http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/t/62630.aspx?pi24527=1