mcbsp rx used in omap3530

	hello ,I have a questions in the omap3530 , when I used mcbsp ,I found my receive  date in DR is wrong,

 but  I can see the CLKR and FSR signals on scope,I used MCBSP1, CLKR and FSR come from internal generation,

I only found register the MCBSPLP_IRQSTATUS_REG which RRDY bit is 1,it means receive buffer occupied locations 

are equal or above the THRSH1_REG value; and MCBSPLP_RBUFFSTAT_REG which RBUFFSTAT bit is zero,it means 

Receive Buffer Status is empty, so I don't understand the Receive Buffer is empty, it is my code ,could you 

find the mistake if  is as my thought, thanks.     

#include "McBSP.h"
#include "PRCM.h"
#include "CONTROL.h"
#include "operations.h"
#include "mcbsp_lib.h"
#include "DMA.h"
#include "dma_lib.h"

#define MY_MCBSP  MCBSP1

int main (void)
{
unsigned int RXBUFF1[16] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0};
// Select clock sources and switch on Switch on the clocks
  cmEnableClock96M(); 
  mcbspEnableIclk(MY_MCBSP);
  mcbspSelectClksSource(MY_MCBSP, INTERNAL_FCLK);
  mcbspEnableFclk(MY_MCBSP);
  
  mcbspSet6Pin(MY_MCBSP);  // Sets McBSP1 to 6 pin mode. 
  
  /////////////////////////////////////////////////////////////
  // reset module
  mcbspReset(MY_MCBSP, 1);  
  
  /////////////////////////////////////////////////////////////
  // Configure  receiver
  mcbspSetRxMode(MY_MCBSP, CLK_INTERNAL, CLKX_DRIVE_FALL,  SYNC_INTERNAL, SYNC_ACTIVE_LOW, HALF_CYCLE, DXENA_OFF, 

XCLK_FREE, FSX_GATED);  

  /////////////////////////////////////////////////////////////
  // Set up frames
  mcbspRxFrameSetup(MY_MCBSP, SINGLE_PHASE, MSB_FIRST, DELAY_0BIT, 4, 1,WORD_8BITS); 
  /////////////////////////////////////////////////////////////
  // Program the Sample Rate generator  
  mcbspSetupSrg(MY_MCBSP, CLKS, CLKS_RISE, SRG_FREE, 32, 8, 255);      

  mcbspSetRxThresh(MY_MCBSP, 127);

 OUT_REGL(CONTROL_PADCONF_MCBSP1_CLKR, 0x01000100);                       // 31:16 = mcbsp1_fsr         15:0 = mcbsp1_clkr
  OUT_REGL(CONTROL_PADCONF_MCBSP1_DX, 0x01000100);	                       // 31:16 = mcbsp1_dr          15:0 mcbsp1_dx 

                   
  CLRBIT_REGL(CONTROL_PADCONF_MCBSP1_CLKX, 0xFFFF);                        // 31:16 = uart3_cts_rctx     15:0 = mcbsp1_clkx
  SETBIT_REGL(CONTROL_PADCONF_MCBSP1_CLKX, 0x0100);                        // 31:16 = uart3_cts_rctx     15:0 = mcbsp1_clkx

 mcbspRemoveResetRx(MY_MCBSP);

mcbspDataGet(MY_MCBSP,RXBUFF1);
return 0；
}