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"The MPU initiates the sleep sequence" , --> what is the sequence?
I believe the sequence you are seeking is given in the flow chart in section 4.12.6.1.3 of the TRM, figure 4-89, this discusses the steps the processor takes in moving to an INACTIVE state such that the power transition can be made to RETENTION or OFF.
jiangao peng said:
"When all conditions are met", --> what is the conditions?
I believe the conditions are basically that the functional and interface clocks are gated, based on the flow chart mentioned above.
2: When OMAP3530 change to sleep mode, Is the SYS_OFF_MODE pin surely low?
The use of the SYS_OFF_MODE pin is enabled through the PRM_VOLTCTRL register's SEL_OFF bit, which must be set to use SYS_OFF_MODE, otherwise the voltage controller sends the equivalent commands through the I2C bus.
The polarity depends on your PRM_POLCTRL register OFFMODE_POL bit setting, if this is 1 than SYS_OFF_MODE will be active high (high when in device off-mode) and if this bit is 1 than SYS_OFF_MODE will be active low (low when in device-off mode).
Hello. I have a pretty basic question about the OMAP3530 SYS_OFF_MODE / TPS65920 nSLEEP1 interface, I think similar to the original question in this posting trail. It appears to me that the default OMAP3530 SYS_OFF_MODE state is low (deasserted) and it asserts high when the OMAP wants the TPS65920 to turn off most of the power to the OMAP (i.e., OMAP wants to go to "sleep"). However, the TPS65920 nSLEEP1 signal defaults to active low. That is, when a low signal is asserted onto nSLEEP1 the PMIC turns off several of the supplies to the OMAP processor. This seems to be in contradiction to the default state of the OMAP SYS_OFF_MODE output. I know the OMAP SYS_OFF_MODE is programmable, so do this mean the software must configure the SYS_OFF_MODE to active low (i.e., "nSYS_OFF_MODE") for the two devices to communicate correctly?
