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OMAP3530 GPMC Burst Transaction Greater than 64 bits

Steven Shade
Prodigy 30 points
Other Parts Discussed in Thread: OMAP3530

 

I'm having some trouble getting the burst mode working for an FPGA device.  The device is configured as a 16-bit NOR flash device with multiplexed address/data.

I can get it to do a burst of 4 words, which is 64-bits. But it looks like the processor core is breaking my 16 word requests into 4x4 word requests.  I think there is some configuration I need to set to get the processor to generate a 16 word burst request to the GPMC module.  The GPMC module looks like it is setup correctly.  How do I get the core processor to generate the burst request longer than 64-bits?

Below is my current GPMC configuration and code that I am using to generate the read instructions.

/*** ARM assembly to generate 16-word16 burst ***/

    asm volatile (
         "ldmia %[in]!, {r3-r10} \n\t"    // read 16 words from address(ss)
         "stmia %[out]!, {r3-r10} \n\t"  // write 16 words to address(dest32)
         :[out]"+r" (dest32)
         :[in]"r" (ss)                        // address(ss) points to GPMC memory location should do a burst of 16-words from GPMC attached device
         :"r3","r4","r5","r6","r7","r8","r9","r10","memory"
    );

/***** Config Below ******/

  /*
    GPMC_CONFIG1: 0x6A001202
    31: WRAPBURST = 0         // synchronous wrapping burst not supported
    30: READMULTIPLE = 1         // Multiple Access = 1 (Burst if synchronous, page if asynchronous)
    29: READTYPE = 1        // Read Synchronous = 1
    28: WRITEMULTIPLE = 0        // Single Access
    27: WRITETYPE = 1        // Write Asynchronous
    26:25: CLKACTIVATIONTIME = 1    // First rising edge of GPMC_CLK at start access time
    24:23: ATTACHDDEVICEPAGELENGTH = 2 // 0 is 4 words, 2 is 16 words
    22: WAITREADMONITORING = 0    // Wait pin is not monitored for read accesses
    21: WAITEWRITEMONITORING = 0    // Wait pin is not monitoried for write accesses
    20: Reserved = 0
    19:18: WAITMONITORINGTIME = 0   // Wait pin is monitored with valid data
    17:16: WAITPINSELECT = 0        // Wait pin is WAIT0
    15:14: Reserved = 0   
    13:12: DEVICESIZE = 1        // 16 bit interface
    11:10: DEVICETYPE = 0        // NOR Flash like device
    9: MUXADDDATA = 1        // Address and data multiplexed attached device
    8:7:6:5 Reserved = 0
    4: TIMEPARAGRANULARITY = 0    // x1 latencies
    3:2: Reserved
    1:0: GPMCFCLKDIVIDER = 2    // GPMC_CLK freq = GPMC_FCLK/2 for 1. GPMC_FCLK/3 for 2
  */
static unsigned int config1 = 0x6B001202;

  /*
    GPMC_CONFIG2:0x001E1803
    31:21: RESERVED = 0
    20:16: CSWROFFTIME = 0x1E  // 20 GPMC_FCLK cycle CS I de-assertion time from start cycle time for write
    15:13: RESERVED = 0
    12:8:  CSRDOFFTIME = 0x18  // 20 GPMC_FLCK CS I de-assertion time from start cycle time for read
    7: CSEXTRADELAY = 0        // CS I Time control signal is not delayed
    6:4: RESERVED = 0
    3:0: CSONTIME = 3       // 2 GPMC_FCLK cycle CS I assertion time from start cycle
  */
static unsigned int config2 = 0x001E1803;

  /*
    GPMC_CONTROL3: 0x00080803
    31:21: RESERVED = 0
    20:16: ADVWROFFIME = 8       // 4 GPMC_FCLK cycle nADV de-assertion time from start cycle time for write
    15:13: RESERVED = 0      
    12:8: ADVRDOFFTIME = 8       // 4 GPMC_FCLK cycle nADV de-assertion time from start cycle for read
    7: ADVEXTRADELAY = 0       // 0 NO - nADV Add Extra Half GPMC_FLCK
    6:4: RESERVED = 0
    3:0: ADVONTIME = 3       // 2 GPMC_FCLK cycle nADV assertion time from start cycle
  */
static unsigned int config3 = 0x00080803;

  /*
    GPMC_CONTROL4: 0x1B091509
    31:29: RESERVED = 0
    28:24: WEOFFTIME = 0x1B       // nWE de-assertion time from start cycle (units = GPMC_FCLK)
    23: WEEXTRADELAY = 0       // nWE Add Extra Half GPMC_FCLK cycle
    22:20: RESERVED = 0
    19:16: WEONTIME = 9       // nWE assertin time from start cycle time (units = GPMC_FCLK)
    15:13: RESERVED = 0
    12:8: OEOFFTIME = 0x15       // nOE de-assertion time from start cycle time (units = GPMC_FCLK)
    7: OEEXTRADELAY = 0       // nOE Add Extra Half GPMC_FCLK cycle
    6:4: RESERVED = 0
    3:0: OEONTIME = 9       // nOE assertion time from start cycle time
  */
static unsigned int config4 = 0x1B091509;

  /*
    GPMC_CONTROL5: 0x05151e18
    31:28: RESERVED = 0
    27:24: PAGEBURSTACCESSTIME = 3 // Delay between successive words in a multiple address
    23:21: RESERVED = 0
    20:16: RDACCESSTIME = 0x15     // Delay between start cycle time and first data valid (GPMC_FCLK cycles)
    15:13: RESERVED = 0
    12:8: WRCYCLETIME = 0x1E       // Total write cycle time (GPMC_FCLK cycles)
    7:5: RESERVED = 0
    4:0: RDCYCLETIME = 0x18           // Total read cycle time (GPMC_FCLK cycles)               
  */
static unsigned int config5 = 0x03151e18;

  /*
    GPMC_CONTROL6:0x92090000
    31: RESERVED = 1
    30:29: RESERVED = 0
    28:24: WRACCESSTME = 0x12     // Delay from start access time to the GPMC_FCLK rising edge
    23:20: RESERVED = 0
    19:16: WRDATAONADMUXBUS = 9   // Specifies on which GPMC_FCLK rising edge the first data
                      // the synchronous burst write is driven in the add/data mux bus
    15:12: RESERVED = 0
    11:8: CYCLE2CYCLEDELAY = 0    // Chip-select high pulse delay between successive accesses (GPMC_FCLK)
    7: CYCLE2CYCLESAMECSEN = 0    // Add CYCLE2CYCLEDELAY between successive accesses to the same CS
    6: CYCLE2CYCLEDIFFCSEN = 0    // Add CYCLE2CYCLEDELAY between successive accesses to a different CS
    5:4: RESERVED = 0
    3:0 BUSTURNAROUND = 0          // Bus turn arround latency (GPMC_FCLK cycles)
  */
static unsigned int config6 = 0x92090000;

  /*
    GPMC_CONTROL7: 0x00000F68
    31:12 RESERVED = 0
    11:8: MASKADDRESS = 0xF       // CS mask address chip-select size of 16 Mbytes
    7: RESERVED = 0
    6: CSVALID = 1              // CS enable must be disabled when writing to BASEADDRESS
    5:0: BASEADDRESS = 0x28          // CS base address bits[2:0] correspond to A26, A25 and A24
                              // CS4 on OMAP3EVM address is 0x28000000
  */

  /* enable cs */
static unsigned int config7 = 0x00000F68;

  • 0
    TI__Guru*** 125430 points

    Steven,

    Let me try to give you some additional insight into what happens when you do a read from external memory at address x.  The sequence of events goes something like this:

    • CPU (Cortex A8) asks L1 data cache controller if it has the contents of address x.  Let's assume it doesn't (L1 cache miss).
    • The L1 cache controller asks the L2 cache controller if it has the contents of address x.  Let's assume again that it does not (L2 cache miss).
    • The L2 cache controller now tells the AXI controller to grab a line of data from external memory starting with address x.
    • The AXI controller issues 64-bit accesses to the L3 interconnect which are serviced by the GPMC.
    • The data lands in L2 cache.
    • The data lands in L1 cache.
    • The CPU gets the data it requested.

    Your case is a little different assuming you don't have cache enabled for the memory range corresponding to your FPGA.  Regardless, the AXI (part of the Cortex A8) is ultimately what issues the read/write commands on the L3 interconnect and there is no way to make it issue transactions that are larger than 64 bits.  If you want to get the best possible performance (maximum bursting) then you need to use a different master on the L3 interconnect to generate the desired burst size.  Typically this would be done with the System DMA.

  • 0 in reply to Brad Griffis
    Prodigy 30 points

     

    Brad,

    I setup the DMA to do the transfer and it works like you suggested.  Thank you for pointing me in the right direction.

    Best Regards,

    Steve

  • 0 in reply to Steven Shade
    Prodigy 20 points

    Hello.

    I'm working whit gumstix overo water (omap3530). I wish to use the GPMC to connect a FPGA. I understand all the proccess to configured the register,  but I don't now how controller the buss address and the data address. How could write/read a region on my FPGA?. How could write/read a specific data on my FPGA?.

    Thanks.

  • 0 in reply to Andres Benavides
    Intellectual 380 points

    Hi Andres,

    See these other useful forum threads for more hints on how to go about working the GPMC with an FPGA.

     

    http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/p/62630/301629.aspx#301629

    http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/p/87612/304617.aspx#304617

  • 0 in reply to Brad Griffis
    Prodigy 160 points

    I have a question along similar lines.  Is it possible to have 2 separate burst generating transactions simultaneously enabled and both pointing to memory on the same GPMC chip select?  If so, what would govern the arbitration between the two?  Is it possible that a GPMC burst might be interrupted and terminate early or will every GPMC burst go to completion?

    The question may be moot in the case of system DMA as the source of both burst transactions becuase it seems that the system DMA has its own arbitration scheme that will allow each burst to go to completion.

  • 0 in reply to Dean Harken
    TI__Guru*** 125430 points

    Dean Harken said:
    Is it possible to have 2 separate burst generating transactions simultaneously enabled and both pointing to memory on the same GPMC chip select?  If so, what would govern the arbitration between the two? 

     

    At the L3 interconnect level only one initiator can write/burst to the GPMC target at any given time.  So in other words, before data can even get to the GPMC there would already be arbitration at the L3 interconnect.  That said, I'd expect these bursts to go to completion.