[OMAP3530] Beginner questions on McBSP

Hi Paul,

I have just tested your files and they work very well, thank you very much.

After reading your code, I have found the reasons why my program does not work, maybe it will be useful to someone.

Here are the mistakes :

- I forgot to select the clock source with CM_CLKSEL1_PLL register

- and the McBSP reset was missing

- RFRLEN2 and XFRLEN2 bits were set to 0

and in MCBSPLP_XCCR_REG register , EXTCLKGATE bit was set to 1.

Thank you again for your help.

Best regards,

Hello,

I've tested the files of  loopback_example_1 as well.  However, it doesn't work.

Following are my development environment: 

1. Mistral OMAP3530 EVM Rev G Board 

2. CCSv3.3

3. Blackhawk USB 560m JTAG Emulator

4. Mistral_Omap35xx_CortexA8.gel for the ARM

5. sdomap35xx_C64plus.gel for the C64x+

So far, I have no problem to connect the target board with JTAG emulator.  However,

registers of McBSP2 (starting from 0x49022000) are not accessible by JTAG+CCS.

Any hint will be very appreciated.

BR,

Juliann

Julian

The loop back example is setup for McBSP1, did you modify it for McBSP2?

The McBSP clocks need to be enabled before you can read/write to the registers.

Please note that with DIGITAL_LOOPBACK  enabled there will be no activity on the external signals

Paul

Hi Paul,

It looks like an McBSP2 example to me, hence I didn't modify your codes. 
Anyway, my simple program in the following is basically doing the initial
steps as your example.  The line to access McBSP1's PCR register works,
but those to access McBSP2's registers fails.  I saw 0x00000000 in all of
the McBSP2 registers in CCSv3.3 memory winodw either running your codes or
my codes.

By the way, I just found the test program (ITBOK) provided by Mistral didn't
pass the McBSP2 route test, it just did a loopback CODEC test in TPS65950.
I'm wondering there's a hardware failure on Mistral EVM.

Juliann

#define MASK_BIT(bit)    (1 << (bit))
typedef volatile unsigned int * const devPtr;
#define REGISTER_ACCESS(root, offset) *(devPtr)(root + offset)
 

//McBSP1==================================
#define MCBSP1              0x48074000
#define FCLKEN1_CORE        0x48004A00
#define ICLKEN1_CORE        0x48004A10
#define CM_CLKSEL1_PLL      0x48004D40

//McBSP2==================================
#define MCBSP2                        0x49022000
#define CM_FCLKEN_PER       0x48005000
#define CM_ICLKEN_PER       0x48005010

#define CM_AUTOIDLE_PER     0x48005030
#define CONTROL_DEVCONF0    0x48002274

//offset==================================
#define MCBSP_PCR_REG       0x00000048
#define MCBSP_SPCR1_REG     0x00000014
#define MCBSP_SPCR2_REG     0x00000010
#define MCBSP_RCR1_REG      0x0000001C
#define MCBSP_XCR1_REG      0x00000024
#define MCBSP_SRGR1_REG     0x0000002C
#define MCBSP_SRGR2_REG     0x00000028
#define MCBSP_MCR1_REG      0x00000034
#define MCBSP_RCERA_REG     0x00000038
#define MCBSP_XCERA_REG     0x00000040
#define MCBSP_XCCR_REG      0x000000AC    

#define _96M_SRC            0x40
#define EN_MCBSP2           0
#define MCBSP2_CLKS         6

#define PADCONF_MCBSP2_CLKX_FSK      (0x4800213C)
#define PADCONF_MCBSP2_DR_DX         (0x48002140)

void main(void)
{

   REGISTER_ACCESS(CM_CLKSEL1_PLL, 0) |= _96M_SRC; 
  
   //McBSP1
   REGISTER_ACCESS(FCLKEN1_CORE, 0) |= MASK_BIT(9);  //Enable MCBSP1
   REGISTER_ACCESS(ICLKEN1_CORE, 0) |= MASK_BIT(9);  //Enable MCBSP1  
   REGISTER_ACCESS(MCBSP1, MCBSP_PCR_REG) |= MASK_BIT(11);   //FSXM  (1)

   
   //McBSP2   
   REGISTER_ACCESS(CM_FCLKEN_PER, 0)  |= (MASK_BIT(EN_MCBSP2));      //0x1 enable McBSP2 functional clock
   REGISTER_ACCESS(CM_ICLKEN_PER, 0)  |= (MASK_BIT(EN_MCBSP2));      //0x1 enable McBSP2 interface clock
   REGISTER_ACCESS(CM_AUTOIDLE_PER,0) |= (MASK_BIT(EN_MCBSP2));      //0x1 McBSP2 auto clock
   REGISTER_ACCESS(CONTROL_DEVCONF0, 0) &= ~(MASK_BIT(MCBSP2_CLKS)); //0x0: CLKS is from PRCM functional clock 
  
   //Pin and Pad settings for McBSP2.
   (*(volatile unsigned int *)PADCONF_MCBSP2_CLKX_FSK) &=0xFFF8FFF8;
   (*(volatile unsigned int *)PADCONF_MCBSP2_DR_DX) &= 0xFFF8FFF8; 

   
   //test McBSP2 registers
   REGISTER_ACCESS(MCBSP2, MCBSP_PCR_REG)   |= MASK_BIT(11);  //FSXM  (1)
   REGISTER_ACCESS(MCBSP2, MCBSP_SPCR2_REG) |= MASK_BIT(9);   //free running mode
   REGISTER_ACCESS(MCBSP2, MCBSP_RCR1_REG)  |= MASK_BIT(6); 

}

Juliann

The example I posted was actually for McBSP2.

The EVM used to test my code is configured with X-Loader 1.42 and U-Boot 2008.10 (now with the ITBOK code included).

I boot the EVM to the u-boot prompt and then download the code from CCS.

How are you booting the board? Can you use CCS to change any McBSP register values?

How does the ITBOK audio test fail? Was there simply no audio or did you get a memory error?

  Paul

Juliann

Can you access/change the registers of the other McBSPs (3,4, & 5)?

Paul

Hi Paul,

The Mistral EVM (Rev. G) has only 3 McBSPs (McBSP1, McBSP2, and McBSP3).
In case of wrong knowledge, I tested registers of all the 5 McBSPs as well.
Only McBSP1 is accessible.  I can change McBSP1's registers value by CCS, seeing

them changing correspondingly, but can't do the same thing to other McBSPs.

I use GEL files to boot the board, then download the code by JTAG from CCS.
(1) Mistral_Omap35xx_CortexA8.gel for the ARM
(2) sdomap35xx_C64plus.gel for the C64x+
The switch seetings for target board are:
(1) SW1 - 1 ON, others OFF  (This enables JTAG connection.)
(2) SW4 - (2,4) ON, others OFF.  another case is: (1,2,3) ON, others OFF.

The JTAG and u-boot (by UART1) cannot work together on Mistral EVM. This
prevent me from doing the same booting procedure as you. I'm wondering
the power domain is not booted properly by GEL files, but my knowledge can't
help me with this.

I got a memory error in ITBOK audio test, then I traced the ITBOK source
codes and found it fall into the routine of CODEC loopback test in TPS65950.
My coworker helped me to rebuild u-Boot following Mistarl's readme.txt
direction by editing the file "include/configs/omap3_evm.h" in u-boot source
directory (see below). We didn't rebuild ITBOK.    
  #define CONFIG_SYS_MALLOC_LEN     (CONFIG_ENV_SIZE + SZ_2M)
This effort still failed the McBSP2 audio test.  

Juliann

Hi Paul,

It seems the interface clocks are not booted up for McbSP2 and McBSP3
except McBSP1 by GEL files.  The McBSP1's base address register (a read
only register) will not be zero anymore when the the ICLKEN1_CORE[9] is
enabled.  I didn't see the same phenomenon on McBSP2/3.

Is Mistral EVM your target board?  Are you using JTAG to download DSP
code from CCS?  Which UART is used for your u-Boot booting?    

Juliann

Hi Paul,

I can access registers of McBSP2, 3 (and others) now.

My settings are:
1. SW1-1  has to be OFF.
2. SW4-(2,4) ON, others OFF.
3. Remove reset and connect relative functions (OnReset, OnTargetConnect)
    from GEL files. Keep setup_memory_map and C64xPlusRelease_FromReset
    functions.
4. Use u-Boot to boot EVM to prompt
5. download DSP codes from CCS by JTAG

So, everything looks fine with McBSP2 now. Thank you.

Juliann

Juliann

That great to hear.

 Paul

Paul,

I am just getting started with McBSP and am trying to interface an OMAP processor (Gumstix Overo) to an ADS1278.  I have never worked with McBSP and was wondering if you could point me towards some documentation and or code that I can use to help get me over the learning curve.

Thanks in advance for your help....

Geoff

Hi Paul,

I am new with OMAP3530 programming and I am working on a BeagleBoard Rev C3. I have a video source on BeagleBoard's Expansion header. I want to recieve a clip from video source to beagle and save it to disk with McBSP1. I think I need to use DMA to write and read McBSP registers but I don't know how to use them. At least if you give me some advice how to port your code to BeagleBoard I'll be gratefull.

Thx in Advance

Fatih

Fatih

Could you elaborate a bit further on what disk is connected to the McBSP? I've not come across this configuration before.

If it's Linux you are using then the example code I've provided in this and other threads will not work as they are designed as standalone examples and should work as-is on the beagle board (but I've not actually tried them on that board).

  Paul

Geoff

OMAP35x Product Page: http://focus.ti.com/docs/prod/folders/print/omap3530.html

Technical Reference Manual: http://focus.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=spruf98i&fileType=pdf

Wiki: http://processors.wiki.ti.com/index.php/AM_McBSP (this is in the AM specific wiki page but McBSP details are the same).

Forum Search: Search for “mcbsp”. Although the basic MCBSP functions are the same there does exist variation in implementation on different parts. The TRM for the OMAP35x will detail what is support in those devices.

Some Examples on the forums:

MCBSP_RX_DMA_1.zip http://e2e.ti.com/cfs-file.ashx/__key/CommunityServer.Components.PostAttachments/00.00.18.63.17/MCBSP_5F00_RX_5F00_DMA_5F00_1.zip

loopback_example_1.zip http://e2e.ti.com/cfs-file.ashx/__key/CommunityServer.Components.PostAttachments/00.00.18.54.58/loopback_5F00_example_5F00_1.zip

Note that these examples are standalone and will probably not work in a Linux environment.

Ask questions! It’s always best to start a new thread for new questions. That way more people get notified of the question.

Yeah i see that they dont work on linux environment :))

So can you explain me how can i work with that codes or  I am gonna use Angstrom or Ubuntu on my Beagleboard with OMAP3530 how can i try these codes onto them?

Thanks in advance

Fozay

Paul,

I am pretty new  basically first time dealing with OMAP Processor and CCSv4.x . I tried to use your loopback example. It builds successfully, But However, it doesn't load program on target.

Following are my development environment: 

1. Mistral OMAP3530 EVM Rev G Board 

2. CCSv4.x

3. Spectrum Digital USB 510 Plus JTAG Emulator

Thru Multi launcher I can boot the board it has Xloader 1.42 and U-Boot 2008.10.

I am trying to load the program thru CCSv4.x. I am able to connect the target but when I am trying to Debug Active Project it complains about in console.

TMS320C64XP: Error connecting to the target: Error 0x80000260/-1178 Fatal Error during: Execution, Initialization, OCS,  The target does not have a CPU clock.

I am not sure where I am going wrong. is it somehting to do with setting up correct  *.gel file or Target ocnfiguration file.. (*.cxml)...

Please would be able to tell me how you were able to load the program on target and debug it...?

Please any help would be appreciated.

Thanks,

AD

ADD

Attached is a document that I created for setting up and using CCS V4.

In your case you would make the following changes in the target configuration:

 - Connection: Spectrum Digital XDS510USB Emulator
 - Device: MISTRAL_OMAP3530_XDS510USB

This should allow you to connect and download to the target.

  Paul

Paul,

Thanks! I tired the steps as noted in the document. Only thing I changed was instead of Hello World program I used your Loopback example as code.

Bu tI am still getting error in loading the program. Below I have noted what are my environment and steps.

Following are my development environment: 

1. Mistral OMAP3530 EVM Rev G Board 

2. CCSv4.1.2

3. Spectrum Digital USB 510 Plus JTAG Emulator

I creatred the Target Configuration file with

 - Connection: Spectrum Digital XDS510USB Emulator
 - Device: MISTRAL_OMAP3530_XDS510USB

Than I created New Project with your given Loopback example file. I have attached the example. After that I build the project. "binaries were created successfully Ican see the "*.out" file. After that "TI Launch Debbuger" which was successful. After that I connected Target which was successful. After that I execute 'Scripts->OMAP35xx Functions->C64xPlusRelease_FromReset' (based on the given thread - http://e2e.ti.com/support/development_tools/code_composer_studio/f/81/t/49722.aspx?PageIndex=2) After that I tried loading the program (*.out) file. And than I got error saying  Failed to load Program '....*.out' 'on target 'MISTRAL_OMAP3530_XDS510USB_0/Cortex_A8'  "REason : Error found during versification. Ensure the linker command file matches the memory map. Refer to the console View for specific address information."

I have also copied below the console message for the entire process....

Cortex_A8: GEL Output: The code download over AHB is turned OFF.

Cortex_A8: GEL Output: CPU Reset callback function has fired  

Cortex_A8: GEL Output: OMAP 32K Watchdog Timer is disable

Cortex_A8: GEL Output: Setup PRCM clock configuration IIA 

Cortex_A8: GEL Output:  CORE_DPLL_CLK = 663.771 MHz 

Cortex_A8: GEL Output:  CORE_CLK = 331.8855 MHz 

Cortex_A8: GEL Output:  L3_CLK = 165.9427 MHz 

Cortex_A8: GEL Output: MM01: mDDR Samsung K4X51323PC - 512 Mbit(64MB) on CS0, 4M x 32bit x 4Banks

Cortex_A8: GEL Output: SDRC initilization for mDDR_Samsung_K4X51323PC completed 

Cortex_A8: GEL Output: GEL StartUp Complete. 

Cortex_A8: GEL Output: C64x+ release from reset 

Cortex_A8: GEL Output: The code download over AHB is turned OFF.

Cortex_A8: GEL Output: CPU Reset callback function has fired  

Cortex_A8: GEL Output: MMU and Cache are OFF. 

Cortex_A8: GEL Output: The code download over AHB is turned ON.

Cortex_A8: Loader: One or more sections of your program falls into a memory region that is not writable.  These regions will not actually be written to the target.  Check your linker configuration and/or memory map.

Cortex_A8: File Loader: Data verification failed at address 0x00000000 Please verify target memory and memory map.

Error found during data verification.

Ensure the linker command file matches the memory map.

I am ont sure where I am going wrong. Also not sure how to match linker command file which I dont hav eone....? to match with memory map which was automatically created. I am sending you the attached entire project which i am trying to load. Any help would be appreciated.  Alos I have attached the "Target configuration file" and gel files used were ..Mistral_Omap35xx_CortexA8.gel  and sdomap35xx_C64plus.gel.

2781.OMAPWorkspace.zip

 1258.target config file created.zip

Thanks!

AD

AD

I'll look at your files shortly. However, if you do not have a linker command file then this is a problem.

Steps 11 & 12 in the guide creates the linker command file. Look at the end of the "How To" document and you'll find an simple linker command example that will work for these examples.

Once the linker command file is created, re-compile and download your project - Step 13.

Run the example - step 14.

You should not need to run any gel files in addition to those automatically executed as these examples run on the ARM.

Try this and let me know what happens.

  Paul

I added the Command Linker file.  Was able to build the project successfully. After that I clicked on "Green Bug" which states "Debug Active Project".

It didnt prompted any warning but when I see on "DEbug" window. it didnt halted at "main" and instead it halted at "0 c_int00() at boot.asm:200 0x80003444 under "Thread [main] (Running)". And I dont see any other activity on nay windows. I am not sure in what state it is.....? I have attached the image file of the CCSv4 screen after I hit "Green Bug".

Also I wanted to ask question why you mentioned in earlier thread that all examples run on ARM ....? and why cant we do that on DSP.....Why we dont select "C6000" as Project Type and Devic Variant as "C64x+" while creating New Project. Sorry for asking you so many questions but I am pretty new to this processor and development.

Thanks for your help.

AD

AD

When the emulator connects to a runnin host like you show, the simplest thing to do is reset the board and stop the boot process at the u-boot prompt. Now re-download the program to the device and all should be good.

I only mention that these are ARM example since I only developed them on the ARM processor.  For specific DSP help I would start a new thread for your questions and someone with more experienced with the DSP provide the answers.

No problem asking questions, it's a great way to learn!

  Paul

Paul,

Thanks! But I am not sure how to stop the boot process at u-boot prompt...? 

In my project I need to load the program on DSP. McBSP1 on DSP should be able to TX/RX communicate to FPGA.

Thanks,

AD

Paul,

Thanks alot for your example. So I was able to load and run the program on ARM side.

Now I want help in loading program on DSP. Where should I post my question on which forum thread...?

Thanks,

Arti

Arti

Great, I'm glad I could help.

For your DSP question, start a new thread in this forum and you should be good.

  Paul

Paul,

Thanks!! I will try to post new thread on DSP.

One more question If working on ARM only can I work on with more than one McBSP Port. As in what we planning to do here is.

Try to receive at external signal form FPGA at McBSP1 and than send it through McBSP1 tx to FPGA. ( I think I can achieve is just by disabling digital loopback in ur example)

Other test is to routing whatever I send out form McBSP1 I receive it on McBSP2 Rx and what ever I transmit from McBSP3 receive it on McBSP1 rx... but when I am trnsmittin gI am transmitting to FPGA... FPGA side is taken care... I nee dto handle this scenario on ARM side...  any idea to get started would help.

Thanks,

AD

AD

The example is very simple and configures McBSP1 as a 4-pin McBSP which results in synchronous transmit/receive.  I suspect that you would want the 6-pin asynchronous mode for your test With the receivers configured as slave and the transmitter configured as master.. Also, the example transmits then receives, sounds like you will need it the other way around. So, with some modification, you could have the code do what you want.

The more complex example is possible.

McBSP1 master transmitter --> McBSP2 Slave
McBSP3 master  --> McBSP1 Slave receiver.

The McBSP master will source the CLK and Frame Sync.

  Paul