Dear All,
We have made out our AM3505 prototype by reference of Logic Pad AM3517EVM. The GPMC bus devices are: NAND, DDR2 and FPGA. The NAND and DDR2 are tested OK but the FPGA cannot access normally. GPMC is configured as address/data-multiplexed mode to interface with FPGA(Asynchronous RAM) via a address latch.
Now we have below questions need your kindly help:
1. For asynchronous R/W timing, the nADV signal in specifications goes something like this: when the add/data bus is idle, nADV should be in high level, but we found it's kept in low level all the time.
2. During R/W access to FPGA, we found that nADV and nOE have the same width(assertion time). We tried to change the register field in CONFIG2~CONFIG6 to change the width of nADV, nCS, while it is effectiveness. Is there any other register need to be modified simultaneously?
And a question puzzled me all the time: nADV share the same pin out(GPMC_nADV_ALE) with ALE, nADV is low level assertion while ALE is high level assertion, is there any conflict?
Your advice is highly appreciated. Thanks!
Kent
