Using DMA to access NAND-Flash (u-boot)

Ludwig Zenz

Intellectual 820 points

Other Parts Discussed in Thread: AM3517

Hello,

to improve the boot-performance of our am3517 modul i want to set up DMA for NAND-Flash reading.

Without DMA only 2MByte/s can be read from the NAND-Flash.

I have been able to set a the DMA like the example from the reference manual for a RAM to RAM transfer with u-boot.

I tried to modifie this for a NAND-Flash read but then I´ve got a problem with the ECC.

My first approach was to replace the code within nand_read_buf like the following:

/**
* nand_read_buf - [DEFAULT] read chip data into buffer
* @mtd:   MTD device structure
* @buf:   buffer to store date
* @len:   number of bytes to read
*
* Default read function for 8bit buswith
*/
static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
   /*
   int i;
   struct nand_chip *chip = mtd->priv;

   for (i = 0; i < len; i++)
   {
       //buf[i] = *(volatile unsigned char *)( 0x6e000084);
       buf[i] = readb(chip->IO_ADDR_R);
   }
*/
   struct omap3_dma4 *omap3_dma4_base    = (struct omap3_dma4*)OMAP3_SDMA_BASE_ADDR;
   struct nand_chip *chip = mtd->priv;

   /* setting up dma */
   omap3_dma4_base->channel[0].csdp    = DATA_TYPE(DATATYPE_8BIT_SCALAR);
   omap3_dma4_base->channel[0].cen       = 32;
   omap3_dma4_base->channel[0].cfn       = 64;
   omap3_dma4_base->channel[0].cssa   = chip->IO_ADDR_R;
   omap3_dma4_base->channel[0].cdsa   = buf;
   omap3_dma4_base->channel[0].csei   = 1;
   omap3_dma4_base->channel[0].csfi   = 1;
   omap3_dma4_base->channel[0].cdei   = 1;
   omap3_dma4_base->channel[0].cdfi   = 1;
   omap3_dma4_base->channel[0].ccr       = DST_ADDR_MODE(POST_INCR_ADDR_MODE) | SRC_ADDR_MODE(CONSTANT_ADDR_MODE);

   /* start dma*/
   omap3_dma4_base->channel[0].ccr       |= CHA_ENABLE;

   while (omap3_dma4_base->channel[0].ccr   & CHA_ENABLE) { asm volatile("nop"); }
}

Is it possible to get a example how to setup a DMA for NAND-Flash access?

What do i need to change?

Thank You, Regards

Ludwig

over 13 years ago

0 Ludwig Zenz over 13 years ago

Intellectual 820 points

I found the error:

I configured the wrong length with CENi und CFNi. With the right length it works, but ...

... some questions are left:

- what is the best solution for Element-Size and Frame-Size?

- I still do only achieve 3.5 MByte/s during read. Is there a way to achieve a better performance. How do i have to setup dma best?

Regards,

Ludwig

0 AnBer over 13 years ago in reply to Ludwig Zenz

TI__Mastermind 30120 points

Hi Ludwig,

a) Some consideration for using sDMA for GPMC is available on the below forum post. Since OMAP35x/AM35x/AM37x do have a comparable architecture I think most of it will apply.

GPMC burst using sDMA : https://e2e.ti.com/support/processors/f/791/t/105271

Also the following post does point to different threads that help to understand the performance differences when accessing GPMC via CPU or sDMA:
DMA size for GPMC
http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/t/107870.aspx#380798

b) Fast boot i snot only about U-boot. There are other consideration. Please refer to the below wiki pages:
http://processors.wiki.ti.com/index.php/Optimize_Linux_Boot_Time
an older page for DM3x as well:
http://processors.wiki.ti.com/index.php/Boot_Time_Optimization
also ultimately u-boot could be removed

Anthony

0 Ludwig Zenz over 13 years ago in reply to AnBer

Intellectual 820 points

Hi,

Thank you for the links!

I am trying to set up Prefetch:

I want to read a page from a nand-flash, which is connected to CS0 and the base-address is 0x00000000.

Where is the Prefetch FIFO mapped?

I tried to read a long-value from 0x00000000, but this did not work.

It seems that the first 64 Bytes are stored in the Fifo. But than i am not able to read out the data.

Can you give some additional information?

Ludwig

0 Ludwig Zenz over 13 years ago in reply to Ludwig Zenz

Intellectual 820 points

I made some progress on my own, again.

I found out that the fifo is at the address 0x00100000. But I do not understand why.

The base-address in gpmc_config7_0 is configured to 0x00.

When i understand the TRM right, that should be not correct.

Am i missing something?

0 AnBer over 13 years ago in reply to Ludwig Zenz

TI__Mastermind 30120 points

Ludwig,

May be the below post can help to understand what need to be configured and why:
http://e2e.ti.com/support/dsp/omap_applications_processors/f/447/p/123629/581997.aspx#581997

It is for OMAP35x but I guess it should be comparable with AM3517.

Hope it helps.

Anthony

0 Renjith Thomas over 13 years ago in reply to AnBer

Guru 31670 points

Ludwig,

We've done optimization on different TI platforms and has achieved 6-8MB/sec read throughput on NAND and upto 13.5 MB/sec on eMMC. If you are interested please get in touch with us. We are also specialized in boot up time optimization.

-Renjith

www.pathpartnertech.com

0 Ludwig Zenz over 13 years ago in reply to Renjith Thomas

Intellectual 820 points

Thank You for your response.

I think i´ve got i right now. I achieve about 6.5MB/sec so it seems there is not much to improve left.

regards,

Ludwig

0 Krunal Patil over 13 years ago in reply to Ludwig Zenz

Genius 3120 points

Hello Ludwig Zenz,

Can you please post your patch? That will certainly help to people like me who might like to improve the boot time.

Regards,

Krunal

0 Ludwig Zenz over 13 years ago in reply to Krunal Patil

Intellectual 820 points

Hello Krunal,

i made boottest with my configuration with nand-prefetch. In about 20 times from 1000 times booting a kernel crc error occurs. This is really a strange behavior.

If this error occurs, there is always a kernel read error at the offset 0x00251E1C from the kernel-offset. This behavior does not change if you write the kernel to another location in the nand flash (so it is no nand-flash problem).

I made a .tar.gz File of the required code-files:

nand_prefetch.tar.gz

(http://e2e.ti.com/members/1791104/files/nand_5f00_prefetch.tar.gz.aspx)

I started with my changes within the file nand_base.c in the function nand_read_buf(). I think it is not the best way i did it, but one of the easiest to integrate dma and prefetch.

Maybe you can get some useful information from the code or you can tell me what i am doing wrong.

I switched back to the former configuration because this code was not reliable.

Regards,

Ludwig

0 AnBer over 12 years ago in reply to Ludwig Zenz

TI__Mastermind 30120 points

Hi Ludwig,

I think that some work were done to support DMA for NAND in u-boot. Please refer to the below post: https://e2e.ti.com/support/processors/f/791/t/179481

It might be a good starting point.

It assumes that U-boot/SPL (from SDK 5.x) is used and not the xloader from the older SDK version.

Anthony

0 MURALI KRISHNA DAMA over 11 years ago in reply to Ludwig Zenz

Prodigy 60 points

Hi Ludwig,

As you mentioned about the CRC errors for 20 times out of 1000 attempts of booting. The reason for the same could be small faults in implementation of prefetch.

The only reason for the problem will be the mismatch between the no of bytes read and available at any point of time. because, if no control on the number of bytes to be available at the time of reading from prefetch engine (fifo size of 64) one will have any number of bytes to be read in fifo (below 64). In such cases if the implementation is done to read all 64 bytes at a time ( Just for example) it will be end of with last byte to be read recusively to fill the gap.

So, one should cautiously implement the code for all the conditions in transfers.

Regards
Murali Krishna Dama

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Using DMA to access NAND-Flash (u-boot)