EXTINTn (nNMI external interrupt) of AM335x

Hi,

I have a similar question.

Basically I like to do a quick processing (for example turning on a LED) inside the NMI interrupt handler in the Linux kernel. Can you advise where in the kernel source tree that I can find this handler, or how to register my handler in the board-am335xevm.c board init file ?

I am using the sitara-linuxsdk-sdg-05.03.02.00 on the TMDXEVM3358 eval board.

- Thomas

I'm wondering about this as well.  In the TRM EXTINT_N or nNMI is only mentioned as a CortexM3 interrupt.

The BeagleBone takes PMIC_INT, inverts it and connects it to this pin.  However, I can't see that it is used anywhere.  In fact I don't see interrupts being supported at all by the current tps65217 PSP driver.

Does anyone at TI have insight into how this signal can be used?

I'm not sure if anyone is still interested in this but I think I may understand what's going on here.

As I posted previously, the only mention of NMI or EXTINT_N in the TRM is as Interrupt #1 for the Cortex M3.  The Cortex M3 is dedicated to Power Management/Wakeup duties according to 8.1.1.4 of the TRM.  As I understand it, the CortexM3 is only active when the Cortex A8 is in a Suspend/Sleep state.  If the M3 receives an interrupt from any of the WKUP domain peripherals it will wake up the Cortex A8 and shut itself down.

I believe that the NMI signal can only be used as a dedicated WKUP interrupt to bring the Cortex A8 out of a suspend/sleep state.  From the documentation it does not seem like this interrupt can be handled directly in software.  Perhaps it is best used as an alternative to the EXT_WAKEUP pin (which I think is only effective in powering on from RTC-only mode).

Regards,
Ali

As previously mentioned in this forum post, the EXTINTn input is sourcing the internal signal named nNMI.

The internal signal name seems to indicate it is an active low non-maskable interrupt, but that is not the case.

The AM335x Silicon Errata contains an advisory that describes how this input is inverted on the first silicon revision and is active high.  This may be corrected in the next silicon revision so you should consider this when designing a PCB that may need to support both silicon versions.

The interrupt input is also maskable like all other ARM Cortex-A8 interrupts.  This interrupt input is connected to the ARM Cortex-A8 interrupt number 7 as described in the ARM Cortex-A8 Interrupts section of the AM335x Technical reference Manual.

Regards,
Paul

Thanks for the information Paul.  I guess I was completely off-base, but that's what happens when you try to figure things out based on outdated documentation (was looking at spruh73c which had INT7 reserved).

Regards,

Ali

Hi, there:

I was try to make the same interrupt NMI working in the AM335x.

I set the irq type is low or high, in both condition I receive the interrupt all the time. Do I need to set something else in order to make it work?

Thank you!

Jin

FYI:

I found a patch which uses the AM335x NNMI pin, connected to the TPS65217B PMIC_INT (as per BeagleBone).  This allows reading the PMIC push button status.

https://groups.google.com/forum/?fromgroups#!topic/beagleboard/umJLdbn4pkA

Note irq_num=7 as mentioned in previous posts.

Also note the PG2.1 silicon changes the polarity on nNMI, from the TRM (spruh73h.pdf):

1.2.7 Changed Polarity of Input Signal nNMI (Pin EXTINTn)
See Section 6.3, ARM Cortex-A8 Interrupts and Errata Advisory 1.0.6.
PG1.0: nNMI input signal is active high.
PG2.x: nNMI input signal is active low.

I'm not sure how the inversion is handled in Linux, but I noticed that the patch mentioned in my previous post (i.e. [PATCH] tps65217: Enable KEY_POWER press on AC loss / PWR_BUT) requests a "level low" irq:

irq_set_irq_type(tps65217->irq, IRQ_TYPE_LEVEL_LOW);

Hi Paul,

I understand that the EXTINTn input events work like the GPIO0 bank events and can wake up the device from the inactive power modes except the RTC-only mode. Is my understanding correct?

Which of  the edge sensitive or the level sensitive is the EXTINTn input events detection?

Best regards,

Daisuke

This is not true.  EXTINTn is not a wake-up source.  Wake-up sources are listed in the TRM Wakeup Sources/Events section.

This terminal is an active high level sensitive interrupt input on silicon revision 1.0, but was changed to be an active low level sensitive interrupt input on silicon revisions 2.x.

Regards,
Paul

Hi Paul,

Thank you for your reply.

Best regards,

Daisuke

Hi Paul,

EXTINTn is not a Non-Maskable Interrupt. GPIO0 bank inputs are Maskable Interrupts and can not ensure the interrupt generation.

What can be used in substitution for NMI?

Best regards,

Daisuke

Hi Jin,

I have the same result as you. The interrupt is received all the time (1000/sec).

Did you get this working correctly?

Paul

Hi, Paul:

My issue is that I was using the first rev chip, it has a problem, the polarity need to be reversed. It is described in the errata released by TI. It is fix in the later rev. You can try to change the polarity of the pin to see if it helps. If this is not help, I remember I configure the pin mux as GPIO pin. But try the polarity first, if it doesn't help I can send you my configuration later.

Jin

Hi Jin,

Thank you for the help.  I am using a first revision chip.  

Do you mean for me to change the polarity in hardware or software?

I think my hardware polarity is correct because the interrupt does not trigger until I drive the pin high.  Then the interrupt stops when I drive the pin low.  But the problem is that the interrupt occurs constantly when the pin is high.

We also have a second revision chip and it has the same behaviour for the constant interrupt, but I will verify this again today.

I would like to try your configuration as well.  If you could send it to me that would be great.

Thank you for your help,

Paul