Phy GigaEthernet RTL8211E on AM3359 board doesn't work

John

Can you provide kernel boot up logs?
Is the phy connected to EMAC 0 or EMAC 1?

Regards
Mugunthan V N

Hi,John

Thanks for your reply.

The phy is connected to RGMII1 directly.I think the RGMII1 is EMAC0

here is my connection,RGMII1 interface:

I modifed board-am335xevm.c as following

/* Module pin mux for rgmii1 */
static struct pinmux_config rgmii1_pin_mux[] = {
{"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
{"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
{"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
{"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
{NULL, 0},
};

static void rgmii1_init(void)
{
setup_pin_mux(rgmii1_pin_mux);
return;
}

static void __init am335x_eth_init(void)
{
rgmii1_init();
am33xx_cpsw_init(1);
}

static void __init am335x_evm_init(void)
{
.........................

am335x_i2c0_init();
am335x_eth_init();
...........................
}

The address of phy is 001,I modified the am33xx_cpsw_slaves in arch\arm\mach-oma\devices.c:

static struct cpsw_slave_data am33xx_cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_id = "0:01",  // RTL8211E address
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_id = "0:02",
},
};

I have modified MAC_MII_SEL register as following:

#define RGMII_MODE_ENABLE 0x3A

__raw_writel(RGMII_MODE_ENABLE,
AM33XX_CTRL_REGADDR(MAC_MII_SEL));

Is there someting wrong?What else should I configure with RGMII?

Thanks!

Regards!

The PHY can link to the attached Ethernet device without RGMII working properly and the link status is provided by reading PHY registers with MDIO.

The RGMII timing budget is very tight, so I suspect your design is violating timing requirements.  It is very important you perform timing analysis when designing your system using RGMII.

I’m not a software expert, but I think the drivers in the Linux kernel were written for the Atheros AR8031.  You may need to modify this driver to properly configure the RTL8211E and AM335x to work together.

Regards,
Paul   

Should I modify the driver about  CPSW?

Hi,

Where can I find AM3359 timing  requirements?

In addition,TXD[0:3]、RXD[0:3] and TXCTL have signals. However, RXCTL doesn't have any signals,it is always  low.Why does it happen? 

Peaves

The driver in Linux is phy independent.

John

The internal delay in SoC is disabled in current Linux Kernel and it needs to be enabled in Phy if needed. You can refer to the following patch in which AR8031 internal delay is enabled
http://arago-project.org/git/projects/?p=linux-am33x.git;a=commit;h=e1b08eedb60cf482795427b9341f456122773522

with regards
Mugunthan V N

Hi,

Thanks  Mugunthan and Paul.

I  have found AM3359 RGMII timing parameters.And I shoud verify the RXCTL' signal.

Paul,you said my  code had some internal AM335x resistors enabled which may be conflicting with any external resistors,could you point out clearly?

I have disable AM3359 internal delay mode by writing MAC_MII SEL register to 0x3A,as following:

#define RGMII_MODE_ENABLE 0x3A

__raw_writel(RGMII_MODE_ENABLE,
AM33XX_CTRL_REGADDR(MAC_MII_SEL));

RTL8211E has no registers that could be configured to delay TXC and RXC ,it only has two pin named TXDLY and RXDLY which used to configure TXC and RXC to 2ns delay.

However,I pull up the two pin to high  to make TXC and RXC delay 2ns.It doesn't work as well.