I have been evaluating the C5502 for an application that requires the use of an audio compression algorithm. The algorithm is too large to fit in the internal DARAM memory of the C5502, so I mapped it to the external SDRAM that is part of the ezdsp5502 eval board. The variables used by the algorithm also consume too much space for internal DRAM, so they are also placed in external SDRAM. Unfortunately, the performance of the 300MHz C5502 is an order of magnitude slower than the same algorithm running on a C5515 which has enough internal memory to accomodate both the algorithm code and the variables. I have enabled the instruction cache on the C5502, which helps to some degree. But the performance is still far below what is acceptable for my project.
Question: Is the lack of a data cache on the C5502 a major bottleneck for this device? It appears that if your data variable space is too large to fit in the internal memory of the C5502, you are out of luck. Can someone from TI weigh in this? I need a 300MHz DSP solution for my application and the C5502 appeared to be a cost effective solution (about half the price of the OMAP-L138). However, after tinkering with it for a while, it now appears to have a major achilles heel (no data cache).
