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Difference between VC5505 and C5505

Hi,

Does anyone know the difference between VC5505 and C5505? We are using VC5505's data sheet when drawing the schematics, but notice the C5505 is released recently. It seems the C5505 is a bug-fixed version, but we would like to confirm that C5505 is pin to pin compatible with VC5505.

Thanks

Shen

  • Really the only major differences I was able to see in the pinouts between VC5505 and C5505 were two LDOI pins F13 and F14 that were not supported in VC5505 and labeled as DSP_LDOI and USB_LDOI. Also the pins needed for the dedicated SDRAM and mSDRAM are added, these pins were labeled as Reserved in the VC5505 pin layout.

  • Indeed the VC55xx parts are not completelly pin to pin comcatible with the C55xx parts. Other than that, here are the improvements on the C550xA from VC550x:

    1)  Power up sequencing (Core first and then I/O) is not required in the C5504A/C5505A.

    2) SAR reset bit (bit2) of the PRCR register(0x1C05) has been added.

    3)“Divide-by-4” added to the PLL output divider.

    4)  mSDRAM Support

                   –         Available in C5504A/C5505A, was not available in C5504/C5505.

    5)  DMA Double Buffering Capability

                   –         Not possible to support double buffering (ping-pong buffer) in C5504/C5505.  DMA needs to be configured by CPU at every new DMA.  This could cause data loss at high transfer data rate.

                   –         A ping-pong buffer has been added in C5504A/C5505A.

     6) Word/Byte swap issue (Advisory 1.4.1)

                   –         DPORT word swap removed

                   –         Endianess of EMIF changed to big endian (hardcoded)

                   –         Endianess of MMC/SD changed to big endian (software controllable)

                  –         Endianess of USB DMA changed to big endian (hardcoded)

    7)  RTC positive compensation did not work for compensation values that are multiples of 10 (Advisory 1.4.2).  This has been fixed in C5504A/C5505A.

    8)  Invalid I2S OUERRFL Error Report at First Frame has been fixed (Advisory 1.4.3).

    9)  DMA in H/W Sync Mode, Auto Reload Bit Overrides Enable Bit has been fixed (Advisory 1.4.6).

    10) DMA:  Hardware Event can trigger DMA data transfer in S/W control mode has been fixed (Advisory 1.4.7).

     

    Note:  The advisories mentioned above are with reference to the VC5505/04 Errata (SPRZ281A).

     

  • Mariana, Thans a lot for the information.

    Shen