XDS100V2 gel script issue

I am currently running a custom board with OMAP L138 and XDS100 emulator. With a gel script. I am running into a  error shown below

ARM9_0: GEL: Error while executing OnTargetConnect(): Target failed to write memory at 0x01C11100.

 If I comment the code out, it throws an error for the same memory location. The Gel script is a modified one from Logic PD. This error shows up in the

 device_PLL0() method.

The register that the emulator cannot write to is PLL0_PLLCMD. Below is a portion  of the gel. \

This only happens when using a xds100V2. It runs smoothly when using a xds510.

I appreciate any help.

device_PLL0(unsigned int CLKMODE, unsigned int PLLM, unsigned int POSTDIV,unsigned int PLLDIV1, unsigned int PLLDIV2, unsigned int PLLDIV3, unsigned int PLLDIV7 ) {

   unsigned int i=0;

   /* Clear PLL lock bit */
   CFGCHIP0 &= ~(0x00000010);

   /* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR */
   PLL0_PLLCTL &= ~(0x00000020);

   /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 for Freon */
   PLL0_PLLCTL &= ~(0x00000200);

   /* Set PLLEN=0 to put in bypass mode*/
   PLL0_PLLCTL &= ~(0x00000001);

   /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
   for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}

   /* Select the Clock Mode bit 8 as External Clock or On Chip Oscilator*/
   PLL0_PLLCTL &= 0xFFFFFEFF;
   PLL0_PLLCTL |= (CLKMODE << 8);

   /*Clear PLLRST bit to reset the PLL */
   PLL0_PLLCTL &= ~(0x00000008);

   /* Disable the PLL output*/
   PLL0_PLLCTL |= (0x00000010);

   /* PLL initialization sequence
   Power up the PLL by setting PWRDN bit set to 0 */
   PLL0_PLLCTL &= ~(0x00000002);

   /* Enable the PLL output*/
   PLL0_PLLCTL &= ~(0x00000010);

   /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
   for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}

   /*Program the required multiplier value in PLLM*/
   PLL0_PLLM    = PLLM; /* Make PLLMULTIPLEIR as bootpacket*/

   /* Prediv setup -Not required */
   //  PLL0_PREDIV = 0x8000 | PREDIV; /* Make POSTDIV as bootpacket*/

   /*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
   PLL0_POSTDIV = 0x8000 | POSTDIV; /* Make POSTDIV as bootpacket*/

   /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
   while(PLL0_PLLSTAT & 0x1==1){}

   /*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
   PLL0_PLLDIV1 = 0x8000 | PLLDIV1;   /* Make PLLDIV1 as bootpacket, do it for other PLLDIVx to if required*/
   PLL0_PLLDIV2 = 0x8000 | PLLDIV2;
   PLL0_PLLDIV4 = 0x8000 | (((PLLDIV1+1)*4)-1);
   PLL0_PLLDIV6 = 0x8000 | PLLDIV1;
   PLL0_PLLDIV3 = 0x8000 | PLLDIV3;   /* Make PLLDIV3 as bootpacket, do it for other PLLDIVx to if required*/
   PLL0_PLLDIV7 = 0x8000 | PLLDIV7;   /* Make PLLDIV7 as bootpacket, do it for other PLLDIVx to if required*/

   /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
   PLL0_PLLCMD |= 0x1;

   /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
   while(PLL0_PLLSTAT & 0x1==1) { }

   /*Wait for PLL to reset properly. See PLL spec for PLL reset time - This step is not required here -step11*/
   for(i=0; i<PLL_RESET_TIME_CNT; i++) {;}   /*128 MXI Cycles*/

   /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
   PLL0_PLLCTL |= 0x8;

   /*Wait for PLL to lock. See PLL spec for PLL lock time*/
   for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;} /*Make PLL_LOCK_TIME_CNT as boot Packet*/

   /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
   PLL0_PLLCTL |=  0x1;

   /* SET PLL lock bit*/
   CFGCHIP0 |= (0x1 << 4) & 0x00000010;
}

 -Manas