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Continuous capture problem using DM642 Video Port and EDMA

I am attempting to set up the Video Port to acquire 720x480 8-bit BT.656 video data, continuously, using a DM642.  I can almost get it to work, except there is something I just can't get to work correctly.  I want to convert the input 4:2:2 and generate output 4:2:0 frames.  I figure the easiest way to do this for the luminance channel is to use two EDMA parameters, one for each field, and use the index value to interlace the two fields into one, composite frame; essentially, the even rows of the interlaced output frame would come from field 1, while the odd rows would come from field 2.  For the chroma channels, because I only need every other line, I'll just use the field 1 data, which neatly decimates the rows by the required factor of two to realize the 4:2:2 -> 4:2:0 conversion.  Finally, because I need to do this continuously, I want to set up a double-buffered (aka ping-pong) scheme (I may eventually end up with triple-buffered, round-robin, if necessary, but for purposes of this discussion, assume the double-buffer approach.)

To accomplish this scheme, I have set up four EDMA parameter tables for each of the three video planes (e.g. luminance and two chroma); in each case, the four parameter tables correspond to four consecutive fields that are encountered when receiving two consecutive frames.  These tables are linked together in a circle, thus setting up the double-buffer.  Finally, the thinking is to have the EDMA generate an interrupt at the end of every field 2 on the luminence channel to serve as an indicator to the DSP on when it should switch to reading the just filled frame.

So far, it seems the basic concept above is valid, and almost works, but I’ve run into two, probably inter-related, problems.  The first symptoms, other than no and/or bad data, are that the video port is reporting a very large number of FIFO overflows, and hence, a very large number of interrupts are being caused – several hundred per frame! Furthermore, I cannot get what I want from the EDMA - specifically, an interrupt when each complete frame has been transferred into memory; instead, I get either one per row or another number I can’t correlate to anything!

On the FIFO overflows, I am quite confused on these, as I would think the EDMA is fast enough to keep up with the video port!  The four tables for each plane are linked together (the LINK bit is set), and TCINT and TCC fields are set, so it would appear the EDMA should be continually updating its operation properly.  The element size is set to 32-bits, the ELECNT field is set to correspond to one row of pixels – specifically, 720 / 4 = 180 for luminance, or 360 / 4 = 90 for the chroma planes.  The FRMCNT field is set to 239, which is the number of rows per field, minus 1.  So it seems each entry handles exactly one field of the associated plane.  So I cannot understand why the video port is detecting FIFO overflows!  (I am pretty sure the Video Port is programmed for the correct video size.)

The excessive interrupts are another matter.  I originally used the value 0x40ba0002 for the OPT value, which sets the LINK bit and other bits appropriately; however, I got a crazy number of interrupts.  A little investigation in the EDMA manual suggested I try setting the FS bit, but that didn’t seem to work – I am still seeing an interrupt per row!

A typical table looks like this:

OPT: 0x40ba0002
SRC: 0x74000000  <- Video Port 0
CNT: 0x00ef00b4   <- 240 rows, 180 words (4 pixels each)
DST: 0x80800100
IDX:  0x05a00000  <- Skips every other row in destination
RLD: 0x00000630  <- points to next table

Any ideas?

  • Robert,

    First, welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages. Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics.

    Second, there is a DM64x Forum that would be the best place to get answers for questions that particularly deal with the video port and its use. Plus, they will know more basic information about video stuff in general. We will have this thread moved there for your convenience.

    But, I often have something to say even if I do not know the answer for you. So you get my two cents worth and take it as you want.

    It has been several years since I worked with the DM642, but I know that we had video drivers offered for it and they worked. I spent a lot of hours trying to help an engineer who wrote his own video port driver and we never got it working. They hired a new guy who was more hardware oriented like me and he wanted the simlest answer which was to use our drivers. They worked and he went on to complete the project.

    I recommend you get our drivers installed and running to the point where you can see 4:2:2 video coming out, with no FIFO overruns and all the data getting through at your required frame rate.

    Then, modify those drivers to get the changes you need.

    FIFO overrun sounds like you might not be reading all of the data. I am curious towards that because of the 4:2:2-to-4:2:0 scheme you are trying to do. Since you are going from 2 bytes per pixel to 1.5 bytes per pixel, the extra data is going somewhere or being overwritten or being left behind in the FIFO which would lead to overflows.

    I could not pick out from your explanation what you are doing with that extra chrominance from field 2. What are you doing with that extra data?

    Not knowing anything about your product, quality issues are hard to talk about. But I do want to mention that high-quality video products use smoothing and combining algorithms for converting interlaced video to progressive non-interlaced. The luminance frame created by interleaving two fields has issues with edges when there is motion in the video. The chrominance created from 4:2:2 to 4:2:0 conversion also goes through a conversion algorithm for those products.

    Regards,
    RandyP

  • Hi RandyP,

    RandyP said:
    Second, there is a DM64x Forum

    I didn't realize that - thanks!

    RandyP said:
    I recommend you get our drivers installed and running to the point where you can see 4:2:2 video coming out, with no FIFO overruns and all the data getting through at your required frame rate.

    I came across some references to the existence of these drivers yesterday!  I reread my post, and realized I hadn't mentioned that I am revamping the software from the original version that was written years ago, by someone who is no longer at the company; I cannot comment on why the drivers were not used before.  That said, I am very interested in them, but do have a few questions and constraints:

    1. What environment(s) are supported by the drivers?  At this point, we have a binary H.264 encoder library that we are using, and have not found a replacement for it; unfortunately, I have been told that it requires us to use Code Composer Studio 3.1.  The provider of this encoder no longer sells or support it, so we are stuck.  Perhaps it will work with newer versions, but I haven't tried it yet, so the drivers kind of have to work with CCS 3.1...

    2. Where do I get them?

    3. Is source code available?  (This doesn't matter so much if the drivers work with CCS 3.1, but is critical if either I have to do some work to get them to work with newer CCS, or if I cannot use them, seeing how they program the peripherals may well show me the errors in my way...)

    RandyP said:

    FIFO overrun sounds like you might not be reading all of the data. I am curious towards that because of the 4:2:2-to-4:2:0 scheme you are trying to do. Since you are going from 2 bytes per pixel to 1.5 bytes per pixel, the extra data is going somewhere or being overwritten or being left behind in the FIFO which would lead to overflows.

    I could not pick out from your explanation what you are doing with that extra chrominance from field 2. What are you doing with that extra data?

    Yeah, I didn't mention that clearly.  The second chrominance fields are indeed being read, into one non-incrementing word to save memory, so that shouldn't be the source of the overruns...

    RandyP said:
    But I do want to mention that high-quality video products use smoothing and combining algorithms for converting interlaced video to progressive non-interlaced. The luminance frame created by interleaving two fields has issues with edges when there is motion in the video.

    Thanks for the information there.  At this point, I am just trying to get it to work, and determine the processor load vs. video quality at that baseline, before looking at any optimization.  Right now, the processor appears to be ~60% loaded, but I'm hoping that is bloated significantly by the extra (non-useful) interrupts that I am experiencing.

    In summary, I await your responses regarding the drivers, which I would happily use if they will work in our environment.  I am still interested in more insight or answers to my original post (especially if I cannot use the drivers!), as I am concerned that what I'm missing in understanding the VP and EDMA peripherals will lead to future difficulties.

    Thanks!!!

    Bob