SPI0 Boot Issue

mirco bazzani

We have made our own C6748 Board Booting from SPI0 flash M25P64.
Our DSP is TMS320C6748BZWT.
After several second to power up all is working fine.
Sometimes the Boot Fails if we power down and up the board fast.
If we see some strange issues ,we think, in ROM Bootloader D800K006.
We have flashed a simple program that it toggles line continuously (using DSPBIOS) in order to understand if the program
is started.
To solve this problem we have manually insert following fill section in aisgen file created with AISGEN 1.9.

    0x0A, 0x59, 0x53, 0x58, //Fill Command
    0x00, 0x00, 0x80, 0x11, //Address Internal Ram(L2) 11800000 256k
    0x00, 0x00, 0x04, 0x00, //Size On chip Ram (L2)11800000 256k 0x40000
    0x00, 0x00, 0x00, 0x00, //Type
    0x00, 0x00, 0x00, 0x00, //Pattern
    //--
    0x0A, 0x59, 0x53, 0x58, //Fill Command
    0x00, 0x00, 0x00, 0x80, //Address On chip Ram (L3) 0x80000000 128k
    0x00, 0x00, 0x02, 0x00, //Size On chip Ram (L3) 0x80000000 128k 0x20000
    0x00, 0x00, 0x00, 0x00, //Type
    0x00, 0x00, 0x00, 0x00, //Pattern
    //--
    0x0A, 0x59, 0x53, 0x58, //Fill Command
    0x00, 0x00, 0x00, 0xc0, //Address External Ram 0xc0000000 32MB
    0x00, 0x00, 0x00, 0x02, //Size 0x2000000
    0x00, 0x00, 0x00, 0x00, //Type
    0x00, 0x00, 0x00, 0x00, //Pattern

Now it works fine but, for us, the strange is that the internal ROM bootloader appears conditioned by Ram memory content.
when the program doesn't start fine, we have reset the DSP manually but it doesn't start. (we have try to reset it many times...).
The only way to restart it fine, is powering down the board and power it up after several seconds.
I've seen in forum that the ROM Bootloader D800K006 uses only L1D and in some cases L2 Memory.

PS. TSTRST and reset line are maintained low during power up and reset line goes High only when all power are stabilized


1)Are there any way to generate Fill section in AISGEN 1.9 program automatically?
2)What do you think about this solution?
3)can it be a ROM bootloader problem?

Thank's to All

over 14 years ago

0 jc-ti over 14 years ago

TI__Mastermind 27585 points

Can you check a couple of things first?

1) When it fails, connect and run the debug GEL file and see where the PC is and if there are any ROM error messages. Is the code getting stuck in the boot loader or does it always get to your code?

2) So the board always works on the first power on, but subsequent power ons fail if the board is not left off for long enough? What about giving it a reset with power still applied, does that ever fail?

It might be a problem with the SPI flash not working correctly when rapildy powering off/on but we can see once you give the results from above.

Theres no way for AISGen to do section fills, and this definitely should not be required no matter how fast you power on/off.

Jeff

0 mirco bazzani over 14 years ago in reply to jc-ti

Prodigy 50 points

Hi Jeff,
Thank's for fast reply, I've made following tests as you ask and I think program stop loop into rom code.
When Boot Freeze I see that PC
Program Counter (PC) = 0x00713DA0
or
Program Counter (PC) = 0x00713DA2

Filling memory to 0x00, I've explained this in my previous post, the problem is very very reduced but it seldom fail also with this solution.

1) Running OMAPL1x_debug.gel file after boot fail you can see following result
   PS: I've changed #define OSCIN_FREQ 24 to #define OSCIN_FREQ 29 in OMAPL1x_debug.gel
   our clock are running at 29.4912 MHz


C674X_0: GEL Output:
---------------------------------------------
C674X_0: GEL Output: |             Device Information            |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: DEV_INFO_00 = 0x1B7D102F
C674X_0: GEL Output: DEV_INFO_01 = 0x00000000
C674X_0: GEL Output: DEV_INFO_02 = 0x0000000A
C674X_0: GEL Output: DEV_INFO_03 = 0x00000002
C674X_0: GEL Output: DEV_INFO_04 = 0x00000000
C674X_0: GEL Output: DEV_INFO_05 = 0x000003E0
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_07-DEV_INFO_08-DEV_INFO_09-DEV_INFO_10-DEV_INFO_11-DEV_INFO_12 = 0-0-5535825-18-36-34
C674X_0: GEL Output: DEV_INFO_13,DEV_INFO_14,DEV_INFO_15,DEV_INFO_16 = 2,0,0,14952
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_17 = 0x00030003
C674X_0: GEL Output: DEV_INFO_18 = 0x00000000
C674X_0: GEL Output: DEV_INFO_19 =C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output: 0C674X_0: GEL Output:
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_20 = 0x30303864
C674X_0: GEL Output: DEV_INFO_21 = 0x3630306B
C674X_0: GEL Output: DEV_INFO_22 = 0x00000000
C674X_0: GEL Output: DEV_INFO_23 = 0x00000000
C674X_0: GEL Output: -----
C674X_0: GEL Output: DEV_INFO_24 = 0x12022024
C674X_0: GEL Output: DEV_INFO_25 = 0x00547851
C674X_0: GEL Output: DEV_INFO_06 = 0x00000080
C674X_0: GEL Output: DEV_INFO_26 = 0x74D00002
C674X_0: GEL Output:

C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |               BOOTROM Info                |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: ROM ID: d800k006
C674X_0: GEL Output: Silicon Revision 2.0
C674X_0: GEL Output: Boot Mode: SPI0 Flash
C674X_0: GEL Output:
ROM Status Code: 0x00000000
Description:C674X_0: GEL Output: No error
C674X_0: GEL Output:
Program Counter (PC) = 0x00713DA0
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              Clock Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLLs configured to utilize 1.2V square wave input.
C674X_0: GEL Output: ASYNC3 = PLL0_SYSCLK2
C674X_0: GEL Output:
C674X_0: GEL Output: NOTE: All clock frequencies in following PLL sections are based
C674X_0: GEL Output: off OSCIN = 29 MHz. If that value does not match your hardware
C674X_0: GEL Output: you should change the #define in the top of the gel file, save it,
C674X_0: GEL Output: and then reload.
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PLL0 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLL0_SYSCLK1 = 290 MHz
C674X_0: GEL Output: PLL0_SYSCLK2 = 145 MHz
C674X_0: GEL Output: PLL0_SYSCLK3 = 24 MHz
C674X_0: GEL Output: PLL0_SYSCLK4 = 72 MHz
C674X_0: GEL Output: PLL0_SYSCLK5 = 290 MHz
C674X_0: GEL Output: PLL0_SYSCLK6 = 290 MHz
C674X_0: GEL Output: PLL0_SYSCLK7 = 48 MHz
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PLL1 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: PLL1_SYSCLK1 = 261 MHz
C674X_0: GEL Output: PLL1_SYSCLK2 = 130 MHz
C674X_0: GEL Output: PLL1_SYSCLK3 = 261 MHz
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PSC0 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: State Decoder:
C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on)
C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
C674X_0: GEL Output: >3 = Transition in progress
C674X_0: GEL Output:
C674X_0: GEL Output: Module 0:    EDMA3CC (0)        STATE = 3
C674X_0: GEL Output: Module 1:    EDMA3 TC0          STATE = 3
C674X_0: GEL Output: Module 2:    EDMA3 TC1          STATE = 3
C674X_0: GEL Output: Module 3:    EMIFA (BR7)        STATE = 2
C674X_0: GEL Output: Module 4:    SPI 0              STATE = 3
C674X_0: GEL Output: Module 5:    MMC/SD 0           STATE = 2
C674X_0: GEL Output: Module 6:    AINTC              STATE = 3
C674X_0: GEL Output: Module 7:    ARM RAM/ROM        STATE = 3
C674X_0: GEL Output: Module 9:    UART 0             STATE = 2
C674X_0: GEL Output: Module 10:    SCR 0 (BR0/1/2/8) STATE = 3
C674X_0: GEL Output: Module 11:    SCR 1 (BR4)        STATE = 3
C674X_0: GEL Output: Module 12:    SCR 2 (BR3/5/6)    STATE = 3
C674X_0: GEL Output: Module 13:    PRUSS              STATE = 3
C674X_0: GEL Output: Module 14:    ARM                STATE = 0
C674X_0: GEL Output: Module 15:    DSP                STATE = 3
C674X_0: GEL Output:
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output: |              PSC1 Information             |
C674X_0: GEL Output: ---------------------------------------------
C674X_0: GEL Output:
C674X_0: GEL Output: State Decoder:
C674X_0: GEL Output: 0 = SwRstDisable (reset asserted, clock off)
C674X_0: GEL Output: 1 = SyncReset (reset assered, clock on)
C674X_0: GEL Output: 2 = Disable (reset de-asserted, clock off)
C674X_0: GEL Output: 3 = Enable (reset de-asserted, clock on)
C674X_0: GEL Output: >3 = Transition in progress
C674X_0: GEL Output:
C674X_0: GEL Output: Module 0:    EDMA3CC (1)        STATE = 3
C674X_0: GEL Output: Module 1:    USB0 (2.0)         STATE = 2
C674X_0: GEL Output: Module 2:    USB1 (1.1)         STATE = 2
C674X_0: GEL Output: Module 3:    GPIO               STATE = 3
C674X_0: GEL Output: Module 4:    UHPI               STATE = 2
C674X_0: GEL Output: Module 5:    EMAC               STATE = 2
C674X_0: GEL Output: Module 6:    DDR2 and SCR F3    STATE = 3
C674X_0: GEL Output: Module 7:    MCASP0 + FIFO      STATE = 2
C674X_0: GEL Output: Module 8:    SATA               STATE = 2
C674X_0: GEL Output: Module 9:    VPIF               STATE = 2
C674X_0: GEL Output: Module 10:    SPI 1              STATE = 2
C674X_0: GEL Output: Module 11:    I2C 1              STATE = 3
C674X_0: GEL Output: Module 12:    UART 1             STATE = 3
C674X_0: GEL Output: Module 13:    UART 2             STATE = 2
C674X_0: GEL Output: Module 14:    MCBSP0 + FIFO      STATE = 3
C674X_0: GEL Output: Module 15:    MCBSP1 + FIFO      STATE = 3
C674X_0: GEL Output: Module 16:    LCDC               STATE = 2
C674X_0: GEL Output: Module 17:    eHRPWM (all)       STATE = 2
C674X_0: GEL Output: Module 18:    MMC/SD 1           STATE = 2
C674X_0: GEL Output: Module 19:    UPP                STATE = 2
C674X_0: GEL Output: Module 20:    eCAP (all)         STATE = 3
C674X_0: GEL Output: Module 21:    EDMA3 TC2          STATE = 3
C674X_0: GEL Output: Module 24:    SCR-F0 Br-F0       STATE = 3
C674X_0: GEL Output: Module 25:    SCR-F1 Br-F1       STATE = 3
C674X_0: GEL Output: Module 26:    SCR-F2 Br-F2       STATE = 3
C674X_0: GEL Output: Module 27:    SCR-F6 Br-F3       STATE = 3
C674X_0: GEL Output: Module 28:    SCR-F7 Br-F4       STATE = 3
C674X_0: GEL Output: Module 29:    SCR-F8 Br-F5       STATE = 3
C674X_0: GEL Output: Module 30:    Br-F7 (DDR Contr) STATE = 3
C674X_0: GEL Output: Module 31:    L3 RAM, SCR-F4, Br-F6 STATE = 3

2)The board seems to work all times if we power it off for a long time (about 20 sec) and after we made a power on
We mantain low reset about 300ms after power on before start DSP.
I've gived a second reset after this one but result is same the boot fail

I hope this help you to understand what's happen
Thank's
Mirco

0 jc-ti over 14 years ago in reply to mirco bazzani

TI__Mastermind 27585 points

Thanks for the info. The bootloader is hanging in the DDR VTP calibration routine based on the PC.

Check the VTPIO_CTL LOCK bit (0x01E2C000 - bit 7). During reset this bit gets cleared to zero. When the ROM code runs for the first time it will set the LOCK bit to one after VTP calibration is finished. If you rerun the ROM code without a reset, the LOCK bit will still be set and the VTP calibration will hang.

If you find that the LOCK bit is still set after you power cycle your board, that means your reset is not happening correctly. Put a scope on both RESET and TRST and observe the levels before, during, and after power cycling. Both RESET and TRST need to be low for at least 20 ns in order to reset the device and reinitialize all the registers. Your board may have too much capacitance on those pins where they take 20 seconds to discharge, which could be why you are not getting a true reset.

Jeff

0 Ankit Agrawal over 14 years ago in reply to jc-ti

TI__Expert 5390 points

Hi Mirco,

Has your query been resolved? If yes, please click on "Verify Answer" for Jeff's thread or else you can proceed further.

Thanks,

Ankit

0 mirco bazzani over 14 years ago in reply to Ankit Agrawal

Prodigy 50 points

the problem is solved Thank's Jeff TSTRst pin shuld be low during reset.

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SPI0 Boot Issue