How to initialize device without CCS as when you do it with a GEL file

Pablo,

The initializations that are done in the GEL file must be done in your Flash code as part of the booted code. Depending on your boot mode, so initialization may be done in an AIS table while other things might need to be done in functions contained within the booted code once that code starts running.

Please be specific about your boot method.

The bootloader document will explain more about the features available during the boot process.

Regards,
RandyP

Thanks a bunch Randy,

This is the configuration we have in the CFG file when using the AISgen:

Device Type: d800k002 DSP

Boot Mode: SPI1 Flash

Clock Source: Crystal 24 MHz

Configure PLL0

Configure PLL1

Configure DDR

Do you think there is something we don't configure here that could be necessary for configure GPIOs as the GEL file does?

We also configure PINMUX in the booted code, like this:

#define PINMUX0_GPIO_REG       (0)
#define PINMUX0_GPIO_MASK      (0x000F0F0F)
#define PINMUX0_GPIO_VAL       (0x00080808)
#define PINMUX1_GPIO_REG       (1)
#define PINMUX1_GPIO_MASK      (0xFFF00FFF)
#define PINMUX1_GPIO_VAL       (0x88800888)
#define PINMUX2_GPIO_REG       (2)
#define PINMUX2_GPIO_MASK      (0xFFFFFFFF)
#define PINMUX2_GPIO_VAL       (0x44444448)
#define PINMUX4_GPIO_REG       (4)
#define PINMUX4_GPIO_MASK      (0xFF000000)
#define PINMUX4_GPIO_VAL       (0x88000000)
#define PINMUX5_GPIO_REG       (5)
#define PINMUX5_GPIO_MASK      (0x00FFFF00)
#define PINMUX5_GPIO_VAL       (0x00888800)

Is there anything we are doing wrong or anything we are not doing?

Thanks again!

Regards,

PabloM

Pablo,

In your GEL file, there are automatic functions that run. These start with On, such as OnTargetConnect and OnReset. The other functions that are called by these automatic functions will initialize the device for you to make CCS work well and avoid you having to separately run each of those other functions.

For your purposes now, you need to understand what all of those other functions are doing so you can duplicate their operations in the initialization phase of your application when it boots from the SPI1 Flash.

The way I recommend doing this is:

1. Comment out or disable all of the On... functions. I usually add the letter "x" in front of the name, then it will not run automatically. Save the GEL and Reload it through CCS, which must be done to bring in the changes.
2. Set the jumpers for No Boot mode, then in the CCS Debug window disconnect the emulator, press the PORz reset button on the board, and connect the emulator.
3. Use the Scripts menu to manually call the initialization commands needed to get your board ready to run, including PLL, DDR, memory map, and any other steps that were being run by OnTargetConnect.
4. Load your application and run it. If it runs successfully, then you have manually called all of the functions needed for initialization. If it does not run successfully, repeat steps 2 and 3 calling additional functions until you have the right list of functions needed for complete initialization.
5. In your AIS flow and your application initialization code, make sure that all of the functions that you manually called are handled.
6. Re-build your application, change the boot mode back to SPI1 Flash, press PORz, and the application should run correctly.

Regards,
RandyP

If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.

Pablo,

A guru reminded me that PSC is often overlooked in the initialization process. You will find it for sure in the GEL functions if you follow the process above.

Regards,
RandyP

If you need more help, please reply back. If this answers the question, please click  Verify Answer  , below.

Greetings,

Do ascertain that the device configuration write is unlocked before doing any programming.

Something like this

/* DEVICE kickUnlock */
 KICK0R = KICK0R_UNLOCK; 
 KICK1R = KICK1R_UNLOCK; 

etc...

otherwise, you are not programming anything in the device.

Good Luck,

Sam

Hi Randy,

Sorry for not answering this time, I was working in other tasks. Thanks for your answers. I couldn't get it yet... I remind you my problem: I can't configure GPIOs properly when programming the DSP permanently using the flash memory. When I program it connecting it to CCS everything works OK because I use a GEL file to configure it. But there is something in GEL file I don't do properly in the source code or in the .cfg file.

I wanted to know what I have to write in my source code or in the .cfg file (the one I use to create the .bin file with AISGen) to make it work. Now I call this function but it seems to be not enough (that values have been obtained with Pin Setup Utility 1.0.663.7 for Primus):

#define PINMUX0_GPIO_REG       (0)
#define PINMUX0_GPIO_MASK      (0x000F0F0F)
#define PINMUX0_GPIO_VAL       (0x00080808)
#define PINMUX1_GPIO_REG       (1)
#define PINMUX1_GPIO_MASK      (0xFFF00FFF)
#define PINMUX1_GPIO_VAL       (0x88800888)
#define PINMUX2_GPIO_REG       (2)
#define PINMUX2_GPIO_MASK      (0xFFFFFFFF)
#define PINMUX2_GPIO_VAL       (0x44444448)
#define PINMUX4_GPIO_REG       (4)
#define PINMUX4_GPIO_MASK      (0xFF000000)
#define PINMUX4_GPIO_VAL       (0x88000000)
#define PINMUX5_GPIO_REG       (5)
#define PINMUX5_GPIO_MASK      (0x00FFFF00)
#define PINMUX5_GPIO_VAL       (0x00888800)

EVMC6748_pinmuxConfig(PINMUX0_GPIO_REG, PINMUX0_GPIO_MASK, PINMUX0_GPIO_VAL);
EVMC6748_pinmuxConfig(PINMUX1_GPIO_REG, PINMUX1_GPIO_MASK, PINMUX1_GPIO_VAL);
EVMC6748_pinmuxConfig(PINMUX2_GPIO_REG, PINMUX2_GPIO_MASK, PINMUX2_GPIO_VAL);
EVMC6748_pinmuxConfig(PINMUX4_GPIO_REG, PINMUX4_GPIO_MASK, PINMUX4_GPIO_VAL);
EVMC6748_pinmuxConfig(PINMUX5_GPIO_REG, PINMUX5_GPIO_MASK, PINMUX5_GPIO_VAL);

Maybe you know how to solve this problem...

Thank you very much!

Regards,

Pablo

In other words, I don't know how to do step 3 you wrote in your answer:

"Use the Scripts menu to manually call the initialization commands needed to get your board ready to run, including PLL, DDR, memory map, and any other steps that were being run by OnTargetConnect."

I don´t know if I can call the same functions in the GEL from my source code.

Greetings,

The steps in RandyP require that you are connected via JTAG EMU and having Hot menus that you can select and execute individually.

Your app cannot call functions from a .gel file, but you can incorporate similar functions and thier sequence of execution in your app.

Here is a functional C6748_boot that you will have to modify to use for your own hardware

void PSC0_LPSC_enable(unsigned int PD, unsigned int LPSC_num);
void PSC1_LPSC_enable(unsigned int PD, unsigned int LPSC_num);
void PSC1_LPSC_SyncReset(unsigned int PD, unsigned int LPSC_num);
void (*app_start)(void);

extern void C6747_Boot(void)
{
    unsigned int i=0;
    /* Clear IER register */

    asm("        zero b0");

    asm("        mvc b0,ier");

    /* SET UP THE STACK POINTER IN B15.                                       */

    /* THE STACK POINTER POINTS 1 WORD PAST THE TOP OF THE STACK, SO SUBTRACT */

    /* 1 WORD FROM THE SIZE.                                                  */

    asm("      mvkl STACK_BGN,SP");

    asm("      mvkh STACK_BGN,SP");

    asm("      mvkl STACK_LEN - 4,B0");

    asm("      mvkh STACK_LEN - 4,B0");

    asm("      add  B0,SP,SP");

    /* THE SP MUST BE ALIGNED ON AN 8-BYTE BOUNDARY.                          */

    asm("      and  ~7,SP,SP");    /* SET UP THE GLOBAL PAGE POINTER IN B14.                                 */

    asm("      .global $bss");

    asm("      mvkl PAGE_BGN,DP");

    asm("      mvkh PAGE_BGN,DP");

    /* SET UP FLOATING POINT REGISTERS FOR C67 ONLY                           */

    asm("      mvk   0,B3");     /* round to nearest */

    asm("      mvc   B3,FADCR");

    asm("      mvc   B3,FMCR");

    /* INITIALIZE CONTROL REGISTERS (FOR BIOS ONLY)                           */

    asm("      mvk     0,B3");

    asm("      mvc     B3,AMR");    /* addressing mode register */

    asm("      mvc     B3,IER");    /* interrupt enable register */
    asm("      mvc     B3,CSR");    /* control status register */

/* DEVICE kickUnlock */
    KICK0R = KICK0R_UNLOCK; 
    KICK1R = KICK1R_UNLOCK; 

/* HPI enable in WORDMODE */
    CFGCHIP1 = (CFGCHIP1 & ~(CFGHPI_ENA_CU)) | (CFGHPI_ENA_CU);

/* PIMMUX Setup */
    PINMUX0  = PINMUX0_PU;
    PINMUX1  = PINMUX1_PU;
    PINMUX2  = PINMUX2_PU;
    PINMUX3  = PINMUX3_PU;
    PINMUX4  = PINMUX4_PU;
    PINMUX5  = PINMUX5_PU;
    PINMUX6  = PINMUX6_PU;
    PINMUX7  = PINMUX7_PU;
    PINMUX8  = PINMUX8_PU;
    PINMUX9  = PINMUX9_PU;
    PINMUX10 = PINMUX10_PU;
    PINMUX11 = PINMUX11_PU;
    PINMUX12 = PINMUX12_PU;
    PINMUX13 = PINMUX13_PU;
    PINMUX14 = PINMUX14_PU;
    PINMUX15 = PINMUX15_PU;
    PINMUX16 = PINMUX16_PU;
    PINMUX17 = PINMUX17_PU;
    PINMUX18 = PINMUX18_PU;
    PINMUX19 = PINMUX19_PU;

/* PSC0 Setup */
    PSC0_LPSC_enable(PD0, LPSC_EDMA_CC0);
    PSC0_LPSC_enable(PD0, LPSC_EDMA_TC0);
    PSC0_LPSC_enable(PD0, LPSC_EDMA_TC1);
    PSC0_LPSC_enable(PD0, LPSC_EMIFA);
    /* PSC0_LPSC_enable(PD0, LPSC_SPI0); */
    /* PSC0_LPSC_enable(PD0, LPSC_MMCSD0); */
    /* PSC0_LPSC_enable(PD0, LPSC_UART0); */
    PSC0_LPSC_enable(PD0, LPSC_SCR0);
    PSC0_LPSC_enable(PD0, LPSC_SCR1);
    PSC0_LPSC_enable(PD0, LPSC_SCR2);
    /* PSC0_LPSC_enable(PD1, LPSC_DSP); */

    /* PSC1 Setup */
    PSC1_LPSC_enable(PD0, LPSC_EDMA_CC1);
    /* PSC1_LPSC_enable(PD0, LPSC_USB20); */
    /* PSC1_LPSC_enable(PD0, LPSC_USB11); */
    PSC1_LPSC_enable(PD0, LPSC_GPIO);
    PSC1_LPSC_enable(PD0, LPSC_UHPI);
    /* PSC1_LPSC_enable(PD0, LPSC_EMAC); */
    PSC1_LPSC_enable(PD0, LPSC_DDR);
    /* PSC1_LPSC_enable(PD0, LPSC_MCASP0); */
    /* PSC1_LPSC_enable(PD0, LPSC_SATA); */
    /* PSC1_LPSC_enable(PD0, LPSC_SATA); */
    /* PSC1_LPSC_enable(PD0, LPSC_VPIF); */
    /* PSC1_LPSC_enable(PD0, LPSC_SPI1); */
    /* PSC1_LPSC_enable(PD0, LPSC_I2C1); */
    /* PSC1_LPSC_enable(PD0, LPSC_UART1); */
    /* PSC1_LPSC_enable(PD0, LPSC_UART2); */
    /* PSC1_LPSC_enable(PD0, LPSC_MCBSP0); */
    /* PSC1_LPSC_enable(PD0, LPSC_MCBSP1); */
    /* PSC1_LPSC_enable(PD0, LPSC_LCDC); */
    PSC1_LPSC_enable(PD0, LPSC_EPWM);
    /* PSC1_LPSC_enable(PD0, LPSC_MMCSD1); */
    /* PSC1_LPSC_enable(PD0, LPSC_UPP); */
    /* PSC1_LPSC_enable(PD0, LPSC_ECAP); */
    PSC1_LPSC_enable(PD0, LPSC_EDMA_TC2);
    PSC1_LPSC_enable(PD0, LPSC_SCR_F0);
    PSC1_LPSC_enable(PD0, LPSC_SCR_F1);
    PSC1_LPSC_enable(PD0, LPSC_SCR_F2);
    /* PSC1_LPSC_enable(PD0, LPSC_SCR_F6); */
    /* PSC1_LPSC_enable(PD0, LPSC_SCR_F7); */
    /* PSC1_LPSC_enable(PD0, LPSC_SCR_F8); */
    /* PSC1_LPSC_enable(PD0, LPSC_BR_F7); */
    PSC1_LPSC_enable(PD0, LPSC_SHARED_RAM);

/* PLL0 Setup */
    /* Clear PLL0 lock bit to FREE run*/
    CFGCHIP0 &= ~(0x00000010);

    /* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR */
    PLL0_PLLCTL &= ~(0x00000020);

    /* PLLCTL.EXTCLKSRC bit 9 should be left at 0 */
    PLL0_PLLCTL &= ~(0x00000200);

    /* Set PLLEN=0 to put in bypass mode*/
    PLL0_PLLCTL &= ~(0x00000001);

    /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
    for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}

    /* Select the Clock Mode bit 8 as External Clock*/
    PLL0_PLLCTL &= ~(0x00000100);

    /*Clear PLLRST bit to reset the PLL */
    PLL0_PLLCTL &= ~(0x00000008);

    /* Disable the PLL output*/
    PLL0_PLLCTL |= (0x00000010);

    /* PLL initialization sequence
    Power up the PLL by setting PWRDN bit set to 0 */
    PLL0_PLLCTL &= ~(0x00000002);

    /* Enable the PLL output*/
    PLL0_PLLCTL &= ~(0x00000010);

    /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
    for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}

    /*Program the required multiplier value in PLLM*/
    PLL0_PLLM    = PLL0_M_CU; /* Make PLLMULTIPLEIR as bootpacket*/

    /* Program postdiv ratio */
    PLL0_POSTDIV = 0x8000 | POSTDIV; /* Make POSTDIV as bootpacket*/

    /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
    while(PLL0_PLLSTAT & 0x1==1){}

    /*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
    PLL0_PLLDIV1 = 0x8000 | PLLDIV1;   /* Make PLLDIV1 as bootpacket, do it for other PLLDIVx to if required*/
    PLL0_PLLDIV2 = 0x8000 | PLLDIV2;
    PLL0_PLLDIV3 = 0x8000 | PLLDIV3;   /* Make PLLDIV3 as bootpacket, do it for other PLLDIVx to if required*/
    PLL0_PLLDIV4 = 0x8000 | (((PLLDIV1+1)*4)-1);
    PLL0_PLLDIV6 = 0x8000 | PLLDIV1;
    PLL0_PLLDIV7 = 0x8000 | PLLDIV7;   /* Make PLLDIV7 as bootpacket, do it for other PLLDIVx to if required*/

    /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
    PLL0_PLLCMD |= 0x1;

    /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
    while(PLL0_PLLSTAT & 0x1==1) { }

    /*Wait for PLL to reset properly. See PLL spec for PLL reset time - This step is not required here -step11*/
    for(i=0; i<PLL_RESET_TIME_CNT; i++) {;}   /*128 MXI Cycles*/

    /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
    PLL0_PLLCTL |= 0x8;

    /*Wait for PLL to lock. See PLL spec for PLL lock time*/
    for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;} /*Make PLL_LOCK_TIME_CNT as boot Packet*/

    /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
    PLL0_PLLCTL |=  0x1;

    /* SET PLL0 lock bit*/
    CFGCHIP0 |= 0x00000010;

/* PLL1 Setup */
    /* Clear PLL1 lock bit */
    CFGCHIP3 &= ~(0x00000020);

    /* Set PLLENSRC '0',bit 5, PLL Enable(PLLEN) selection is controlled through MMR */
    PLL1_PLLCTL &= ~(0x00000020);

    /* PLLCTL.EXTCLKSRC bit 9 should be left at 0*/
    PLL1_PLLCTL &= ~(0x00000200);

    /* Set PLLEN=0 to put in bypass mode*/
    PLL1_PLLCTL &= ~(0x00000001);

    /*wait for 4 cycles to allow PLLEN mux switches properly to bypass clock*/
    for(i=0; i<PLLEN_MUX_SWITCH; i++) {;}

    /*Clear PLLRST bit to reset the PLL */
    PLL1_PLLCTL &= ~(0x00000008);

    /* Disable the PLL output*/
    PLL1_PLLCTL |= (0x00000010);

    /* PLL initialization sequence
    Power up the PLL by setting PWRDN bit set to 0 */
    PLL1_PLLCTL &= ~(0x00000002);

    /* Enable the PLL output*/
    PLL1_PLLCTL &= ~(0x00000010);

    /*PLL stabilisation time- take out this step , not required here when PLL in bypassmode*/
    for(i=0; i<PLL_STABILIZATION_TIME; i++) {;}

    /*Program the required multiplier value in PLLM*/
    PLL1_PLLM    = PLL1_M_CU; /* Make PLLMULTIPLEIR as bootpacket*/

    /*If desired to scale all the SYSCLK frequencies of a given PLLC, program the POSTDIV ratio*/
    PLL1_POSTDIV = 0x8000 | POSTDIV; /* Make POSTDIV as bootpacket*/

    /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
    while(PLL1_PLLSTAT & 0x1==1){}

    /*Program the RATIO field in PLLDIVx with the desired divide factors. In addition, make sure in this step you leave the PLLDIVx.DxEN bits set so clocks are still enabled (default).*/
    PLL1_PLLDIV1 = 0x8000 | PLLDIV1;   /* Make PLLDIV1 as bootpacket, do it for other PLLDIVx to if required*/
    PLL1_PLLDIV2 = 0x8000 | PLLDIV2;   /* Make PLLDIV2 as bootpacket, do it for other PLLDIVx to if required*/
    PLL1_PLLDIV3 = 0x8000 | PLLDIV3;   /* Make PLLDIV3 as bootpacket, do it for other PLLDIVx to if required*/

    /*Set the GOSET bit in PLLCMD to 1 to initiate a new divider transition.*/
    PLL1_PLLCMD |= 0x1;

    /*Wait for the GOSTAT bit in PLLSTAT to clear to 0 (completion of phase alignment).*/
    while(PLL1_PLLSTAT & 0x1==1) { }

    /*Wait for PLL to reset properly. See PLL spec for PLL reset time - */
    for(i=0; i<PLL_RESET_TIME_CNT; i++) {;}   /*128 MXI Cycles*/

    /*Set the PLLRST bit in PLLCTL to 1 to bring the PLL out of reset*/
    PLL1_PLLCTL |= 0x8;

    /*Wait for PLL to lock. See PLL spec for PLL lock time*/
    for(i=0; i<PLL_LOCK_TIME_CNT; i++) {;} /*Make PLL_LOCK_TIME_CNT as boot Packet*/

    /*Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode*/
    PLL1_PLLCTL |=  0x1;

    /* SET PLL lock bit*/
    CFGCHIP3 |= 0x00000020;

/* Init EMIFA */
    /* GC5330 chip# 0 */
    EMIF25_ACFG5 = EMIF_A1CR_CU;

/* Init EMIFB (DDR) */

    /* Clear CLK2XSRC */
    CFGCHIP3 &= ~(0x00000080);

    /*Enable the Clock to EMIF3A SDRAM*/
    PSC1_LPSC_enable(0, LPSC_EMIF3A);
    /*If VTP claiberation is enabled , then skip it*/
    if(VTPIO_CTL & (0x00000040))
    {
        // Begin VTP Calibration
        VTPIO_CTL |= (0x00004000);     // Set IOPWRDN bit to enable input buffer powerdown enable mode
        VTPIO_CTL &= ~(0x00000040);  // Clear POWERDN bit (enable VTP)

        // Pulse (low) CLRZ to initiate VTP IO Calibration
        VTPIO_CTL |= (0x00002000);       // Set CLRZ bit
        VTPIO_CTL &= ~(0x00002000);    // Clear CLRZ bit (CLRZ should be low for at least 2ns)
        VTPIO_CTL |= (0x00002000);       // Set CLRZ bit

        // Polling READY bit to see when VTP calibration is done
        while(!((VTPIO_CTL & (0x00008000))>>15)) {}

        VTPIO_CTL |= (0x00000080);        // Set LOCK bit for static mode
        VTPIO_CTL |= (0x00000100);     // Set PWRSAVE bit to save power
    }  // End VTP Calibration

    // Config DDR timings
    DDRCTL               = EMIF_DDRPHYCR_CU;
    EMIF3A_SDCR          = EMIF_SDCR_CU | (0x00808000);  // Ensure tim_unlock bit is set
    EMIF3A_SDTIMR1       = EMIF_SDTIMR1_CU;
    EMIF3A_SDTIMR2       = EMIF_SDTIMR2_CU;
    EMIF3A_SDCR         &= ~(0x00808000); // Clear tim_unlonk bit
    EMIF3A_SDCR2         = 0;
    EMIF3A_SDRCR         = EMIF_SDRCR_CU;

    // Set the DDR2 to syncreset
    EMIF3A_SDRCR |= 0xC0000000;  // Set to self-refresh, enable mclkstop
    /*SyncReset the Clock to EMIF3A SDRAM*/
    PSC1_LPSC_SyncReset(0, LPSC_EMIF3A);

    /*Enable the Clock to EMIF3A SDRAM*/
    PSC1_LPSC_enable(0, LPSC_EMIF3A);

    /* Disable self refresh */
    EMIF3A_SDRCR &= ~(0xC0000000);  // disable self-refresh

    KICK0R = KICK0R_LOCK;
    KICK1R = KICK1R_LOCK;

    /* Jump to App */
    /* Get application start address */
    app_start = (void (*)(void))(APP_START_CU);

    app_start();

}

/*Enable Function for PSC0*/
extern void PSC0_LPSC_enable(unsigned int PD, unsigned int LPSC_num)
{
    if( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) != 0x3 ) {
      *(unsigned int*) (PSC0_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC0_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0003;
      PSC0_PTCMD = 0x1<<PD;

      /*Wait for power state transition to finish*/
      while( (PSC0_PTSTAT & (0x1<<PD) ) !=0) ;

      while( (*(unsigned int*)(PSC0_MDSTAT+4 * LPSC_num) & 0x1F) !=0x3);
    }
}

/*Enable Function for PSC1*/
extern void PSC1_LPSC_enable(unsigned int PD, unsigned int LPSC_num)
{
    if( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) != 0x3 ) {
      *(unsigned int*) (PSC1_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC1_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0003;
      PSC1_PTCMD = 0x1<<PD;

      /*Wait for power state transition to finish*/
      while( (PSC1_PTSTAT & (0x1<<PD) ) !=0) ;

      while( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) !=0x3);
    }
}

/*SyncReset Function for PSC1*/
extern void PSC1_LPSC_SyncReset(unsigned int PD, unsigned int LPSC_num)
{
    *(unsigned int*) (PSC1_MDCTL+4*LPSC_num) = (*(unsigned int*) (PSC1_MDCTL+4*LPSC_num) & 0xFFFFFFE0) | 0x0001;
    PSC1_PTCMD = 0x1<<PD;
    while( (PSC1_PTSTAT & (0x1<<PD) ) !=0) ; /*Wait for power state transition to finish*/
    while( (*(unsigned int*)(PSC1_MDSTAT+4 * LPSC_num) & 0x1F) !=0x1);
}

Good luck,

Sam

BTW, it is for C6748.  I made a typo in C6747.

Greetings,

I failed to mention in here that the basis of this source code is the Gel file provided by the L138/C6748 EVM vendor, modified/corrected to do the SOC initialization when use as part of a secondary boot loader or the full application, regardless of the boot mode.

Good Luck,

Sam

Thank you very much for your answers Sam!!

I tried the code you wrote, adapting it to my case but I had some problems because it entered in some infinite loops... I don't want to change something I don't know and make it worse...

I wanted to ask you if you know how to make an initialization like the one you wrote but only to initialize GPIOs and PINMUX configuration. I aske you that because my problem has only to do with this part. Hope you know something...

Thanks again!!

Pablo

Greetings,

Even if your Pinmux setup to enable the GPIOs is faulty, you should not get hang in any infinite loop of this code.  Notice that the infinite loop are wait loop for the PLLs like this

    /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
    while(PLL0_PLLSTAT & 0x1==1){}

or this

    /*Check for the GOSTAT bit in PLLSTAT to clear to 0 to indicate that no GO operation is currently in progress*/
    while(PLL1_PLLSTAT & 0x1==1){}

 or the PSCs like this

      /*Wait for power state transition to finish*/
      while( (PSC0_PTSTAT & (0x1<<PD) ) !=0) ;

or this

      /*Wait for power state transition to finish*/
      while( (PSC1_PTSTAT & (0x1<<PD) ) !=0) ;

You should be able to grab the CPU with the EMU without loading a GEL file, Reset the CPU, load this code in IRAM, and step through it to determine where your CPU is hanging, whether it is in the PLL init or PSC init.  you may have a bad clocking dividers.

Good Luck, Let us know

Sam

Pablo,

It has been some time since your last post here. Have you been successful with initializing your GPIOs?

If you have been successful, please share here your method. If not, please tell what your current status is or if nothing has changed, yet.

Regards,
RandyP