hello Engineers
I am working on Omap-l138 experimental kit the DSP side (so its equivalent to C6748, I geuss). I am trying to get the EDMA to handle the transmitted data through SPI port.
the data I am sending is a 1D array. I set up the PARAM fields (PARAM 15) and (PARAM 31) for reloading purpose. SPI port configuration is all ok since it outputs data when using the bsl fxn (spi_xfer), but when commenting the fxn to let the DMA handle the transfer nothing comes out neither the clk nor data bits,
here is the code I used and I hope you help me identify the problem
void main (void)
{
SPI_init(SPI0,&spi0_config);
setup_EDMA();
SETBIT(SPI0->SPIINT,1 << 16);//spi EDMA service enable
while(1) {
// SPI_xfer(SPI0,pingSrcBuffer_2,NULL,2400, SPI_HOLD_CLR);
}
}
//-----------------------------
static void setup_EDMA (void)
{
// Clear Event Registers
edmaInit();
// Enable Channel 15 to DSP (Region 1)
EDMA3_0_CC0->DRA[CSL_EDMA3_REGION_1].DRAE|=CSL_EDMA3CC_DRAE_E15_MASK | CSL_EDMA3CC_DRAE_E31_MASK; //SPI0 xmt event
// Initialize PaRAM Transfer Context for Events 10 - 11
init_PaRAM_event15();
init_PaRAM_event31();
// init_PaRAM_event11();
// Enable Channel 15 Event Register and Assign to Queue 0
EdmaEnableChannel(EDMA_chan15,EDMAQNUM_0);
}/* setup_EDMA */
//--------------------------
void edmaInit()
{
edmaCcRegs->ECR = 0xffffffff; // clear events 0 -> 31
edmaCcRegs->EECR = 0xffffffff;
edmaCcRegs->SECR = 0xffffffff; // clear secondary events 0 -> 31
edmaCcRegs->IECR = 0xffffffff; // disable all interrupts
edmaCcRegs->ICR = 0xffffffff; // clear all pending interrupts
}
//----------------------------------
void init_PaRAM_event15 (void)
{
// Reset EDMA PaRAM OPT Register
EDMA3_0_CC0->PARAMSET[EDMA_chan15].OPT = 0x0;
// Config PaRAM OPT (disable chaining, AB_sync)
EDMA3_0_CC0->PARAMSET[EDMA_chan15].OPT =CSL_EDMA3CC_OPT_DAM_MASK | 1<< 12;
// Initialize EDMA Event Src and Dst Addresses
EDMA3_0_CC0->PARAMSET[EDMA_chan15].SRC = (uint32_t)&pingSrcBuffer_2;//dds_txbuf
EDMA3_0_CC0->PARAMSET[EDMA_chan15].DST = (uint32_t)&SPI0->SPIDAT0;//spi0 xmt reg.
// Set EDMA Event PaRAM A,B,C CNT
EDMA3_0_CC0->PARAMSET[EDMA_chan15].A_B_CNT = 2400 << Bcnt_shift | 1;
EDMA3_0_CC0->PARAMSET[EDMA_chan15].CCNT = 1;
// Set EDMA Event PaRAM SRC/DST BIDX
EDMA3_0_CC0->PARAMSET[EDMA_chan15].SRC_DST_BIDX = 0 << 16 | 1;
// Set EDMA Event PaRAM SRC/DST CIDX
EDMA3_0_CC0->PARAMSET[EDMA_chan15].SRC_DST_CIDX = 0x0;
// Set EDMA Event PaRAM LINK and BCNTRLD
EDMA3_0_CC0->PARAMSET[EDMA_chan15].LINK_BCNTRLD = 15 <<16 |(0x43E0) ;//Bcnt=15 bytes
}/* init_PaRAM_event15 */
void init_PaRAM_event31(void)
{
// Reset EDMA PaRAM OPT Register
EDMA3_0_CC0->PARAMSET[EDMA_chan31].OPT = 0x0;
// Config PaRAM OPT (disable chaining, A_sync)
EDMA3_0_CC0->PARAMSET[EDMA_chan31].OPT =CSL_EDMA3CC_OPT_DAM_MASK | 1<< 12;
// Initialize EDMA Event Src and Dst Addresses
EDMA3_0_CC0->PARAMSET[EDMA_chan31].SRC = (uint32_t)&pingSrcBuffer_2;//dds_txbuf
EDMA3_0_CC0->PARAMSET[EDMA_chan31].DST = (uint32_t)&SPI0->SPIDAT0;//spi0 xmt reg.
// Set EDMA Event PaRAM A,B,C CNT
EDMA3_0_CC0->PARAMSET[EDMA_chan31].A_B_CNT = 2400 << Bcnt_shift | 1;
EDMA3_0_CC0->PARAMSET[EDMA_chan31].CCNT = dds_Ccnt;
// Set EDMA Event PaRAM SRC/DST BIDX
EDMA3_0_CC0->PARAMSET[EDMA_chan31].SRC_DST_BIDX = 0 << 15 | 1;
// Set EDMA Event PaRAM SRC/DST CIDX
EDMA3_0_CC0->PARAMSET[EDMA_chan31].SRC_DST_CIDX = 0x0;
// Set EDMA Event PaRAM LINK and BCNTRLD
EDMA3_0_CC0->PARAMSET[EDMA_chan31].LINK_BCNTRLD = 15 <<16 |(0x4E10) ;//Bcnt=15 bytes
}/* init_PaRAM_event31 */
thanks....