• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 1 answer
  • Subscribers 99 subscribers
  • Views 2933 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SYS/BIOS MMU Support Disable

Thomas S
Intellectual 600 points
Other Parts Discussed in Thread: SYSBIOS, TEST2

I had problems accessing periperals until I found out, that sys/bios by default enables the MMU.
I found the source code for that in Mmu.c/Mmu.h. The descriptor table is set in a variable ti_sysbios_family_arm_arm9_Mmu_Module__state__V  (Test2_pe9.c: Project Name is Test2 for ARM9/TMS470) for which the framework reserves statically 16kB of memory.

What are the criterias according which the framework sets up the default descriptor table?
Why are some CPU (ARM) registers mapped and some others not (e.g. GPIO registers)?
How can I influence the descriptor table settings (what is the idea)?

Is there a way of disabling the MMU feature from SYS/BIOS and getting rid of the statically allocated 16kB?

Best regards

Thomas

  • 0
    TI__Mastermind 45025 points

    Hi Thomas,


    The MMU table is directly tied to the Cache module, so if you are using any Cache module (e.g. xdc.useModule('ti.sysbios.hal.Cache') in your *.cfg file) it will cause the Mmu module to be pulled in along with its descriptor table.

    You can get rid of the table by not using Cache in your app.  Can you try removing any useModule("*.Cache") statements from your *.cfg file and see if this works?

    Steve

  • 0 in reply to Steven Connell
    Intellectual 600 points

    Dear Steve

    Thanks for your reply.

    Actually my .cfg file looks like this:

    var Mmu = xdc.useModule('ti.sysbios.family.arm.arm9.Mmu');
    var BIOS = xdc.useModule('ti.sysbios.BIOS');
    Mmu.enableMMU = false;
    Mmu.cachePlatformMemory = false;

    I had to explicitly state to disable the MMU, else SYS/BIOS activates the MMU.

    As you can see I have nowhere used the "Cache" module.

    Other question: Is it possible to disable the cache for the ARM or is it always disabled when I do not use the MMU?
    How can I check if any cache is active between memory and cpu?

    Best regards

    Thomas

  • 0 in reply to Thomas S
    TI__Mastermind 45025 points

    can you try removing the MMU code from your *cfg?

    // var Mmu = xdc.useModule('ti.sysbios.family.arm.arm9.Mmu');
    var BIOS = xdc.useModule('ti.sysbios.BIOS');
    // Mmu.enableMMU = false;
    // Mmu.cachePlatformMemory = false;

    The line Mmu.enableMMU = false; is not enough; the table will still be created.

    Steve

  • 0 in reply to Steven Connell
    TI__Mastermind 30830 points

    The Hwi module used for Arm9 targets pulls in the ti.sysbios.hal.Cache module, which uses the ti.sysbios.family.arm.arm9.Cache module, which pulls in the Mmu module, which unilaterally creates the huge table you're unhappy with.

    The only thing I've thought of to break this chain of events is to bind the ti.sysbios.hal.Cache module to a null Cache delegate:

        var Cache = xdc.useModule('ti.sysbios.hal.Cache');
        Cache.CacheProxy = xdc.useModule('ti.sysbios.hal.CacheNull');

    Unfortunately, this will also have the side effect of disabling cache, which will significantly effect performance.

    Alan

  • 0 in reply to Steven Connell
    Intellectual 600 points

    Hi Steve

    Actually, that is what I had first. But default configuration of SYS/BIOS is MMU activated with this huge TLB.

    So, the green statements set  a flag that is checked by the startup code (Mmu.c), which disables the MMU at runtime. So, therefore the TLB still exists.

    At least interesting would be how to configure the TLB differently (the default settings), since the default settings protect the GPIO registers and other
    hardware modules (in system mode)?

    Thomas

  • 0 in reply to Alan DeMars
    Intellectual 600 points

    Hi Alan

    That's interesting. Although having the cache disabled for my target ablication isn't an option, for testing of my hardware (DDR2 ram) this might be a helpful asset.

    Thanks and best regards

    Thomas