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Configuring McBSP driver in SPI mode using EDMA or Interrupts

sriram garikipati
Prodigy 220 points

Hi,

referring to the thread,..   http://e2e.ti.com/support/embedded/bios/f/355/t/34234.aspx

I am using DM6437 EVM with 1.50 gel file. I have configured the McBSP driver (using versions -- pspdrivers_1_10_03, Bios_5_33_01)  as SPI master in order to communicate with SPI-EEPROM in Interrupt mode.

I am driving the SPI clock at 300Mhz. And generating interrupt for every 8bit of transfer.   It works fine when I am using simple background task with the SPI write task. But I am facing some transmission errors when I integrated the same driver code in the final system( video Encoding) . Where the system shares the SPI events with the other EDMA events via ECM manager. I am suspecting the issue with Interrupt latencies as the SPI driver is very sensitive for underruns.

I am trying to configure seperate HWI interrupts for the SPI driver using the same McBSP driver's (_DDA_McBSP_RegisterInt()) like

       hwiattrs.arg =(Arg)chan;
       HWI_dispatchPlug(evt, (Fxn)intIsr, (-1) , &hwiattrs);
       ECM_dispatchPlug(evt, (ECM_Fxn)intIsr, &hwiattrs);
       HWI_eventMap(5,evt);
       C64_enableIER(1<<5);

I am able to generate the interrupts but after 4 bytes of transfer it fails.

can any body please help me in configuring the the McBSP driver for seperate HWI or solving the above problem.

Also If possible can any body( Sadeep et al) provide the sample code to run the EDMA mode of the McBSP driver  for SPI communication.

Many Thanks,

regards,

Sri

 


 

 

  • 0
    TI__Expert 7290 points

    Hi,

    sriram garikipati said:

    I am driving the SPI clock at 300Mhz. And generating interrupt for every 8bit of transfer.   It works fine when I am using simple background task with the SPI write task. But I am facing some transmission errors when I integrated the same driver code in the final system( video Encoding) . Where the system shares the SPI events with the other EDMA events via ECM manager. I am suspecting the issue with Interrupt latencies as the SPI driver is very sensitive for underruns.

    Have you tried with the SPI clock less than the 300Mhz, to confirm that the issue is the clash of the SPI interrupt with the EDMA events?  can you try different SPI clock starting from 1 Mhz?

    sriram garikipati said:

    Also If possible can any body( Sadeep et al) provide the sample code to run the EDMA mode of the McBSP driver  for SPI communication.

    Modify the structure PSP_mcbspDevParams mcbsp_deviceparams{ ....} in the application, to make it work in DMA mode.

    Please refer the chapter 5 of the document “<>\pspdrivers_1_10_03\packages\ti\sdo\pspdrivers\drivers\mcbsp\docs\BIOS_McBSP_Driver_UserGuide.pdf” for more info.

    Regards,

    Sandeep K

  • 0 in reply to Sandeep Krishnaswamy
    Prodigy 220 points

    Hi Sandeep,

    Many thanks for reply.

    I apologize for  mentioning 300Mhz.. Its 300Khz. I have tested for upto 900Khz.

    Also ,I found some code alignment issue in my code. After that the code started to work fine with H.264 encoder code. Seems there may not be an issue with encoder QDMA..

    I have not included any drivers(I.e VPFE,VPBE ) in the above test. But when I started integrating these drivers and some task sleep for encoder task.. the issue pop up again. I.e After some time ...the SPI tranmission task blocked on a semaphore( I have not digged in detail in to semaphore type).

    I tried changing McBSP code to generate interrupts for both Tx and Rx interrupts seperately, increasing the waits after each serial tranmist request(GIO_submit). But no use.  I am  just speculating,.... problem may not be just QDMA/EDMA but with the multiple interrupts  generated by the different drivers I.e VPFE,VPBE,EDMA.  resulting in SPI  task starvation.. don't know.. am I missing anything.?

    Now, I have basic question.. how much reliable to use interrupt based SPI tranmission in a complex system like video encode + decode?. I am not concerned about the the overhead of context switching , I know it will be much higher as generating 1 interrupts for each byte of transmission.

    regards,

    Sri

     

  • 0 in reply to sriram garikipati
    TI__Mastermind 18320 points

    Sriram,

    I have moved this thread over to the DaVinci forum in hopes that you will be able to get further information from the system experts there...