DSP/BIOS: Pros and Cons?

Dear Randy,

RandyP said:

Determinism is a vague concept for a cache-based system with interrupts. DSP/BIOS does not insert additional non-deterministic behavior, and can in fact improve the determinism of your debug code by the use of LOG_printf rather than printf.

I understand that purely determinism is hard to define. I need to study more on this.

Sincerely,

Zheng

Dear Amit,

I am very sorry for failing to notice the answer, there is probably something wrong with the Outlook or I have mistakenly marked the email notification as "read" before opening it.

Thanks very much for the detailed answer and I might ask some other questions in new threads.

Regards,

Zheng

Dear Randy,

RandyP said:

Determinism is a vague concept for a cache-based system with interrupts.

What happens if cache are disabled? Can they be disabled?  I have found that in creating a custom RTSC platform the default values of L1D, L1P and L2 cache are all zero (please see this post), can this work? If the code/EVM could work when caches are all set to zero, plus disabling all interrupts, do we then have the strict determinism here?

Zheng

Dear Randy,

However sophisticated the logic is, essentially all processors, as well as their constituent components, are silicon implementation of discrete state machines. For any particular given sequence of input, all intermediate state transitions, consequently the processing time, and eventually the output result, are all determined as a causal chain of consequences which is an a priori existence before the real execution. It is therefore like a "time-invariant" system: no matter the input is given today or a year later, as long as the environment (chip, memory, etc.) is initialized to the same state, every step will be the same like the playback of a recorded frame sequence.

Cache is processor's immediate surroundings and the cache management unit is like her handmaiden, which adds an intermediate logistic layer for improved performance. However, cache management unit itself is still a state machine and its introduction only results in a more efficient one, but still a state machine. It is therefore will still have the same a priori deterministic and "time-invariant" property the same as a system without cache. This is why I couldn't agree fully with your "vague concept" description.

In real application, of course we will not always have the same repeated input. However, if the input is already known beforehand (for example, the HD Avatar film), and assuming no external interrupt (button press, etc.), then the output can still be predicted before the execution.

Sincerely,
Zheng

Dear Randy,

It is simply great to get your confirmation on 2 :)

A bit further, I think this reproducibility is actually an advantage of digital (binary) system over analog system. In the physical world we will always have errors, but as long as it is within the error margin (in voltage, etc.) of logic gates, we would still get the correct 0 or 1 result.

To set the status of a discrete state machine in this sense is hence much easier than for a continuous causal system, since for them we have thermal noise, EMI and others factors that are hard to manage. Errors in a continuous system can propagate, be amplified and affect a much larger area, but for binary system we can almost always eliminate small errors (within the margin) at the first logic gate.

Sincerely,

Zheng

Dear Randy,

You are still correct with the "vague determinism" characterization.

In different context the word "determinism" has different meanings. What I meant in my initial post belongs more properly to the analysis of complexity on a hypothetical machine with a uniform memory (equal access speed to all parts) rather than a hierarchical structure, so the analysis is relatively simple.

The introduction of memory hierarchy and caching mechanism add another intermediate layer between CPU and DDR2 memory. The cache management unit has its own algorithm to make decisions based on the situation (percentage of cache that has been filled, etc.), and this will make it more complicated for the analysis than the previous simplistic model. Some instructions and memory reference might be done completely by mapping to the cache's copy of memory content, but many times not, so additional load and wait time could be incurred. This would definitely complicate the analysis and whether "absolute determinism" is guaranteed would be harder to judge than for uniform memory case (I had a look at the first volume of TAOCP by Dr. Knuth, page 126, section 1.3.1, and it seems that his hypothetical MIX machine contains three types of memory: 1) register 2) memory cells 3)magnetic tape units. There doesn't appear to be a cache layer.).

Thanks very much for all the replies in this thread which helped me to truly understand the use of cache.


Zheng

Dear Randy,

I have found that there could be a number of complications when cache is enabled and they all made program's behavior difficult to predict. Could you have a look at this post Memory hierarchy related questions?

Zheng

Why do you care about prediction?

I just want to know these. They are important.

Zheng