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add 1080p H.264 encode demo on DM6467T EVM board

xiao jacky
Intellectual 315 points
Other Parts Discussed in Thread: TVP7002, THS7353, THS7303, THS8200, CDCE949, LMH1980

I want to add 1080p30 h264 encoder demo on the TI DM6467T EVM board. 

but TI only provided 720p30 h264 encode demo on the TI DM6467T EVM board.

I know that TI have released one 1080p30(input 1080i,but encode as 1080p) HP encode demo(DM6467 1080p30 H264 Encoder  Demo-Beta-Linux-x86-Install) runs at 675 MHz of DM6467 EVM.

my question is below:

 I wonder if Linux kernal tvp7002 driver (linux-davinci-staging.tar.gz in the dvsdk_3_10_00_19) have supported 1080p video capture now.  

if linux driver support 1080p capture,  so  I only   need to  modify the 720P "encode" demo that is included with the DVSDK to allow encoding of 1080 video?  

thanks. 

  • 0
    TI__Genius 16810 points

    Due to a limitation in the TVP7002 sync separator, a separate VSYNC input is requried to support 24/30Hz progressive input formats.  A simple hardware solution that has been used to extract VSYNC from SOGOUT is attached.   Your EVM may requrie modification to include this work-around.

    Below are the TVP7002 register settings that we have used with this hardware modification for 1080p24 and 1080p30 input support.

     

    DATASET_NAME,"TVP7002_1080p-24Hz Work-Around  20-bit 4:2:2 with embedded syncs - 74.25MHz "

    //TVP7002

    //                                    Reg, Data

    WR_REG,TVP7000,0x01,0x01,0xAB // H-PLL FEEDBACK DIVIDER MSB  2750

    WR_REG,TVP7000,0x01,0x02,0xE0 // H-PLL FEEDBACK DIVIDER LSB 

    WR_REG,TVP7000,0x01,0x03,0x90 // H-PLL CONTROL              

    WR_REG,TVP7000,0x01,0x04,0x80 // H-PLL PHASE SELECT         

    WR_REG,TVP7000,0x01,0x05,0x32 // CLAMP START                

    WR_REG,TVP7000,0x01,0x06,0x20 // CLAMP WIDTH                

    WR_REG,TVP7000,0x01,0x07,0x2C // HSOUT OUTPUT WIDTH         

    WR_REG,TVP7000,0x01,0x08,0x3C // BLU FINE GAIN           

    WR_REG,TVP7000,0x01,0x09,0x3C // GRN FINE GAIN           

    WR_REG,TVP7000,0x01,0x0A,0x3C // RED FINE GAIN           

    WR_REG,TVP7000,0x01,0x0B,0x80 // BLU FINE OFFSET         

    WR_REG,TVP7000,0x01,0x0C,0x90 // GRN FINE OFFSET    Black level = 64     

    WR_REG,TVP7000,0x01,0x0D,0x80 // RED FINE OFFSET         

    WR_REG,TVP7000,0x01,0x0E,0x3E // SYNC CONTROL 1  HSYNC from SOG, VSYNC from VS_IN           

    WR_REG,TVP7000,0x01,0x0F,0x22 // H-PLL AND CLAMP CONTROL    

    WR_REG,TVP7000,0x01,0x10,0x5D // SYNC ON GREEN THRESHOLD    

    WR_REG,TVP7000,0x01,0x11,0x40 // SYNC SEPERATOR THRESHOLD   

    WR_REG,TVP7000,0x01,0x12,0x01 // H-PLL PRE-COAST            

    WR_REG,TVP7000,0x01,0x13,0x00 // H-PLL POST-COAST           

    WR_REG,TVP7000,0x01,0x15,0x47 // OUTPUT FORMATTER  embedded syncs 4:2:2         

    WR_REG,TVP7000,0x01,0x16,0x11 // MISC CONTROL 1             

    WR_REG,TVP7000,0x01,0x17,0x50 // MISC CONTROL 2             

    WR_REG,TVP7000,0x01,0x18,0x01 // MISC CONTROL 3             

    WR_REG,TVP7000,0x01,0x19,0x00 // INPUT MUX SELECT 1         

    WR_REG,TVP7000,0x01,0x1A,0xCF // INPUT MUX SELECT 2         

    WR_REG,TVP7000,0x01,0x1B,0x77 // BLU AND GRN COARSE GAIN 

    WR_REG,TVP7000,0x01,0x1C,0x07 // RED COARSE GAIN         

    WR_REG,TVP7000,0x01,0x1D,0x00 // FINE OFFSET LSB            

    WR_REG,TVP7000,0x01,0x1E,0x10 // BLU COARSE OFFSET       

    WR_REG,TVP7000,0x01,0x1F,0x10 // GRN COARSE OFFSET       

    WR_REG,TVP7000,0x01,0x20,0x10 // RED COARSE OFFSET       

    WR_REG,TVP7000,0x01,0x21,0x39 // HSOUT OUTPUT START         

    WR_REG,TVP7000,0x01,0x22,0x08 // MISC CONTROL use MAC_EN            

    WR_REG,TVP7000,0x01,0x26,0x80 // AUTO LEVEL CONTROL ENABLE  

    WR_REG,TVP7000,0x01,0x28,0x53 // AUTO LEVEL CONTROL FILTER  

    WR_REG,TVP7000,0x01,0x29,0x08 // ADC TEST CONTROL       

    WR_REG,TVP7000,0x01,0x2A,0x83 // FINE CLAMP CONTROL         

    WR_REG,TVP7000,0x01,0x2B,0x00 // POWER CONTROL              

    WR_REG,TVP7000,0x01,0x2C,0x50 // ADC SETUP                  

    WR_REG,TVP7000,0x01,0x2D,0x00 // COARSE CLAMP CONTROL       

    WR_REG,TVP7000,0x01,0x2E,0x80 // SOG CLAMP CONTROL           

    WR_REG,TVP7000,0x01,0x2F,0x0C // RGB COARSE CLAMP CONTROL   

    WR_REG,TVP7000,0x01,0x30,0x04 // SOG COARSE CLAMP CONTROL   

    WR_REG,TVP7000,0x01,0x31,0x5A // AUTO LEVEL CONTROL PLACEMENT

    WR_REG,TVP7000,0x01,0x34,0x13 // MACROVISION STRIPPER WIDTH  use 13 with external 27MHz REFCLK

    //WR_REG,TVP7000,0x01,0x34,0x07 // MACROVISION STRIPPER WIDTH use  7 with internal REFCLK

    WR_REG,TVP7000,0x01,0x35,0x00 // VSYNC ALIGNMENT            

    WR_REG,TVP7000,0x01,0x36,0x02 // SYNC BYPASS                

    WR_REG,TVP7000,0x01,0x3D,0x06 // LINE LENGTH TOLERANCE      

    WR_REG,TVP7000,0x01,0x3F,0x0F // VIDEO BANDWIDTH CONTROL

       

    //embedded syncs

    WR_REG,TVP7000,0x01,0x40,0x07 // AVID Start  263 (236+27)  for SOG filter difference

    WR_REG,TVP7000,0x01,0x41,0x01 // AVID Start

    WR_REG,TVP7000,0x01,0x42,0x8B // AVID Stop  2187 (AVID start + 1920 + 4)

    WR_REG,TVP7000,0x01,0x43,0x08 // AVID Stop

       

    WR_REG,TVP7000,0x01,0x44,0x03 // VBLK START LINE OFFSET (F0)

    WR_REG,TVP7000,0x01,0x45,0x03 // VBLK START LINE OFFSET (F1)

    WR_REG,TVP7000,0x01,0x46,0x2D // VBLK DURATION (F0)         

    WR_REG,TVP7000,0x01,0x47,0x2D // VBLK DURATION (F1)         

    WR_REG,TVP7000,0x01,0x48,0x00 // F-BIT START LINE OFFSET (F0)

    WR_REG,TVP7000,0x01,0x49,0x00 // F-BIT START LINE OFFSET (F1)

     

     

    END_DATASET

     

    ////////////////////////////////////////////////////////////////////////////////

     

    BEGIN_DATASET  // Appended by WinVCC v5.24.  Saved all registers.

     

    DATASET_NAME,"TVP7002_1080p-30Hz Work-Around  20-bit 4:2:2 with embedded syncs - 74.25MHz "

     

    //TVP7002

    WR_REG,TVP7000,0x01,0x01,0x89 // H-PLL FEEDBACK DIVIDER MSB 

    WR_REG,TVP7000,0x01,0x02,0x80 // H-PLL FEEDBACK DIVIDER LSB 

    WR_REG,TVP7000,0x01,0x03,0xE0 // H-PLL CONTROL              

    WR_REG,TVP7000,0x01,0x04,0x80 // H-PLL PHASE SELECT         

    WR_REG,TVP7000,0x01,0x05,0x32 // CLAMP START                

    WR_REG,TVP7000,0x01,0x06,0x20 // CLAMP WIDTH                

    WR_REG,TVP7000,0x01,0x07,0x2C // HSOUT OUTPUT WIDTH         

    WR_REG,TVP7000,0x01,0x08,0x3C // BLU FINE GAIN           

    WR_REG,TVP7000,0x01,0x09,0x3C // GRN FINE GAIN           

    WR_REG,TVP7000,0x01,0x0A,0x3C // RED FINE GAIN           

    WR_REG,TVP7000,0x01,0x0B,0x80 // BLU FINE OFFSET         

    WR_REG,TVP7000,0x01,0x0C,0x90 // GRN FINE OFFSET    Black level = 64     

    WR_REG,TVP7000,0x01,0x0D,0x80 // RED FINE OFFSET         

    WR_REG,TVP7000,0x01,0x0E,0x3E // SYNC CONTROL 1     HSYNC from SOG, VSYNC from VS_IN       

    WR_REG,TVP7000,0x01,0x0F,0x22 // H-PLL AND CLAMP CONTROL    

    WR_REG,TVP7000,0x01,0x10,0x5D // SYNC ON GREEN THRESHOLD    

    WR_REG,TVP7000,0x01,0x11,0x40 // SYNC SEPERATOR THRESHOLD   

    WR_REG,TVP7000,0x01,0x12,0x01 // H-PLL PRE-COAST            

    WR_REG,TVP7000,0x01,0x13,0x00 // H-PLL POST-COAST           

    WR_REG,TVP7000,0x01,0x15,0x47 // OUTPUT FORMATTER  embedded syncs 4:2:2          

    WR_REG,TVP7000,0x01,0x16,0x11 // MISC CONTROL 1             

    WR_REG,TVP7000,0x01,0x17,0x50 // MISC CONTROL 2             

    WR_REG,TVP7000,0x01,0x18,0x01 // MISC CONTROL 3             

    WR_REG,TVP7000,0x01,0x19,0x00 // INPUT MUX SELECT 1         

    WR_REG,TVP7000,0x01,0x1A,0xCF // INPUT MUX SELECT 2         

    WR_REG,TVP7000,0x01,0x1B,0x77 // BLU AND GRN COARSE GAIN 

    WR_REG,TVP7000,0x01,0x1C,0x07 // RED COARSE GAIN         

    WR_REG,TVP7000,0x01,0x1D,0x00 // FINE OFFSET LSB            

    WR_REG,TVP7000,0x01,0x1E,0x10 // BLU COARSE OFFSET       

    WR_REG,TVP7000,0x01,0x1F,0x10 // GRN COARSE OFFSET       

    WR_REG,TVP7000,0x01,0x20,0x10 // RED COARSE OFFSET       

    WR_REG,TVP7000,0x01,0x21,0x39 // HSOUT OUTPUT START         

    WR_REG,TVP7000,0x01,0x22,0x08 // MISC CONTROL 4  Use MAC_EN bit           

    WR_REG,TVP7000,0x01,0x26,0x80 // AUTO LEVEL CONTROL ENABLE  

    WR_REG,TVP7000,0x01,0x28,0x53 // AUTO LEVEL CONTROL FILTER  

    WR_REG,TVP7000,0x01,0x29,0x08 // ADC TEST CONTROL       

    WR_REG,TVP7000,0x01,0x2A,0x83 // FINE CLAMP CONTROL         

    WR_REG,TVP7000,0x01,0x2B,0x00 // POWER CONTROL              

    WR_REG,TVP7000,0x01,0x2C,0x50 // ADC SETUP                  

    WR_REG,TVP7000,0x01,0x2D,0x00 // COARSE CLAMP CONTROL       

    WR_REG,TVP7000,0x01,0x2E,0x80 // SOG CLAMP CONTROL          

    WR_REG,TVP7000,0x01,0x2F,0x0C // RGB COARSE CLAMP CONTROL   

    WR_REG,TVP7000,0x01,0x30,0x04 // SOG COARSE CLAMP CONTROL   

    WR_REG,TVP7000,0x01,0x31,0x5A // AUTO LEVEL CONTROL PLACEMENT

    WR_REG,TVP7000,0x01,0x34,0x13 // MACROVISION STRIPPER WIDTH  use 13 with external 27MHz REFCLK

    //WR_REG,TVP7000,0x01,0x34,0x07 // MACROVISION STRIPPER WIDTH use  7 with internal REFCLK

    WR_REG,TVP7000,0x01,0x35,0x00 // VSYNC ALIGNMENT            

    WR_REG,TVP7000,0x01,0x36,0x02 // SYNC BYPASS                 

    WR_REG,TVP7000,0x01,0x3D,0x06 // LINE LENGTH TOLERANCE      

    WR_REG,TVP7000,0x01,0x3F,0x0F // VIDEO BANDWIDTH CONTROL  

     

    //embedded syncs

    WR_REG,TVP7000,0x01,0x40,0x07 // AVID Start  263 (236+27)  for SOG filter difference

    WR_REG,TVP7000,0x01,0x41,0x01 // AVID Start

    WR_REG,TVP7000,0x01,0x42,0x8B // AVID Stop  2187 (AVID start + 1920 + 4)

    WR_REG,TVP7000,0x01,0x43,0x08 // AVID Stop

         

    WR_REG,TVP7000,0x01,0x44,0x03 // VBLK START LINE OFFSET (F0)

    WR_REG,TVP7000,0x01,0x45,0x03 // VBLK START LINE OFFSET (F1)

    WR_REG,TVP7000,0x01,0x46,0x2D // VBLK DURATION (F0)         

    WR_REG,TVP7000,0x01,0x47,0x2D // VBLK DURATION (F1)         

    WR_REG,TVP7000,0x01,0x48,0x00 // F-BIT START LINE OFFSET (F0)

    WR_REG,TVP7000,0x01,0x49,0x00 // F-BIT START LINE OFFSET (F1)

    TVP7002 1080P30Hz Work Around.pdf
  • 0 in reply to Larry Taylor
    Intellectual 315 points

     thank  for your  reply.

     but  I found  one test code (video_hd_playback_1080p ,download from http://support.spectrumdigital.com/boards/evmdm6467t/revc/)  for DM6467T EVM.

    It  looks like  support  1080p on the DM6467T EVM.  

    ----------------------------------------------------

    /*

     *  Video Setup

     *

     */

     

    /* Video Decoder */

    #include "tvp7002.h"

    #include "ths7353.h"

     

    /* Video Encoder */

    #include "adv7343.h"

    #include "ths7303.h"

    #include "ths8200.h"

     

    /* Video Processor */

    #include "vpif.h"

     

    /* Clocking */

    #include "cdce949.h"

     

    /* ------------------------------------------------------------------------ *

     *  video_hd_playback_1080p( )                                              *

     * ------------------------------------------------------------------------ */

    Int16 video_hd_playback_1080p( )

    {

        Int16 errors = 0, a, i;

        Int16 mode = MODE_HDTV_1080P;

    char buf[4];

        

        /* Enable TVP7002 */

        errors |= enable_tvp7002( );

     

        /* Input Filter */

        errors |= ths7353_setup( mode );

     

        /* Input Decoder */

        errors |= tvp7002_setup( mode );

     

        /* Input Video Capture */

        errors |= vpif_hd_capture( mode );

     

        /* Output Video Display */

        errors |= vpif_hd_display( mode );

     

        /* Output Encoder */

        errors |= ths8200_setup ( mode );

     

        /* Output Filter */

        errors |= ths7303_setup( mode );

     

        return errors;

    }

      

      

     

  • 0 in reply to xiao jacky
    TI__Genius 16810 points

    Regarding the TVP7002, 1080p60Hz can be supported without the work-around.   The TVP7002 sync separater  limitation is with the low frame rate (24Hz and 30Hz) progressive formats.  The 1080p DM6467 support mentioned does not specify frame rate.  The DM6467 EVM schematic shown on the Spectrum website does not have the TVP7002 hardware work-around requried for 1080p24Hz and 1080p30Hz support, so this would have to be added for TVP7002 30Hz support.. 

  • 0 in reply to Larry Taylor
    Prodigy 180 points

    Hi,

    What is the frame rate of your work-around for TVP7002?

    Currently, I applied your work-around to our IP camera system which consists of Zoom module, TVP7002, and DM368.

    What frame rate is measured by your DM6467T platform?

  • 0 in reply to sylee@probedigital.com
    TI__Genius 16810 points

    I have not tested this on the DM6467 platform, but I am attaching TVP7002 setups for 1080p24,25, and 30Hz.  The TVP7002 output frame rate should be the same as the 1080p input.

    TVP7002 1080p24_25_30Hz Work-around 422 embedded syncs 081910.zip
  • 0 in reply to Larry Taylor
    TI__Mastermind 30120 points

    Hi Larry,

    The DM368 EVM has a TVP7002 and supports 1080i30 but not 1080p30. I looked at the schematics of the EVM and the HW workarround you mentioned is not implemented which might explain why:
    http://support.spectrumdigital.com/boards/evmdm368/revg/

    Do you think that the workaround can be made on the EVM directly? How good do you think the design of workaround should be? For example do you think it requires a little extra PCB?

    Thanks and best regards,

    Anthony

  • 0 in reply to AnBer
    TI__Genius 16810 points

    Anthony,

    It looks like modifying the EVM will not be easy.  The TVP H/VSync inputs are tied to ground.

    The LMH1980 sync separator or equivalent would be the best soution for this.  The exteramnl sync sync separator would then supply discreted HSync and VSync to the TVP7002.  There were some issues encountered with the simple RC filter souiltion that showed up with some 25Hz formats.