L1/L2 IRAM + Cache settings for DM8168 DSP in XDC tools (xdctools_3_20_08_88)

Don't have your answer... but want to better understand what you're trying to do.

First, you clipped off the footnotes to table 2-24.

Footnote (4) indicates that, from the C674x POV, addrs 0x1000 0000 - 0x10FF FFFF are mapped to 0x0000 0000 - 0x00FF FFFF.  Working through all that indirection, it does look like IRAM as XDC defines it (0x1080 0000) really is where it is in table 2-24 (0x0080 0000).

I can't explain whether one addr is "better" than another, though.

Can you explain what you're trying to do?  Are you configuring that L2 as all memory and no cache, and trying to use it as IRAM?  And what are you using that IRAM for - code, data or both?  I'm not sure we've validated SysLink's ability to load code to that internal memory (maybe that's why one addr is better than another... if the A8 can see/load it?!?).  Are you putting a heap into that IRAM that you want DSKT2 to allocate from for algs?

We can look into this a bit, but I want to understand your use case so we address your actual use case.

Chris

Hmm... after digging through the bug database a little, it looks like this is already filed as an issue.  SDOCM00081803 - "Slaveloader fails on dsp internal memories".

Not too many users of that DSP just yet, RV... and most are using L2 as all cache.  Looks like you're bleeding some more by living on the cutting edge.  :(

Chris

I have two problems:

1. I have DSP assembly code, that I would like to run from IRAM. I have link.cmd. When I build codec server, this places the code in IRAM ( 128kb set as RAM). This resets DSP. Now I know it is a bug.

Are you putting a heap into that IRAM that you want DSKT2 to allocate from for algs?

Answer is yes, but it is not working. That is the second problem. 

When ACPY3 is passed scratch memory allocated from DSKT2 in IRAM (as well as L1D SRAM) , the DMA transfer from/to DDR3 using acpy3 runs, but acpy3 read/writes by EDMA controller is invalid.  

The document above (table 2-19) shows  EDMA  controller need to access DSP memory at an offset of 0x3000 0000. Footnote on Table 2-24 doesn't address this translation at all.

Per this post, looks like address offset 0x3000 0000 to any IRAM buffer pointer (passed to acpy3)  is needed for DMA to work.

Will a config change to DMAN3 accomplish this?

 

 

RV

I tried this code:

   

    ACPY3_activate(inst->dmaHandles[0]);

    ACPY3_activate(inst->dmaHandles[1]);

    dmaParams.transferType = ACPY3_1D1D;

    dmaParams.elementSize = 1280;

    dmaParams.numElements = 1;

    dmaParams.srcElementIndex = 0;

    //don't care for 1D1D transfer

    dmaParams.dstElementIndex = 0;

    dmaParams.waitId = 0;

 

    for (i = 0; i != 480; i++)

    {

        dmaParams.srcAddr = inExtNewVideo;

        dmaParams.dstAddr = inIntNewVideoCurrent;

        ACPY3_configure(inst->dmaHandles[0], &dmaParams, 0);

        ACPY3_start(inst->dmaHandles[0]);

        ACPY3_wait(inst->dmaHandles[0]);

        inExtNewVideo += 1280;

        dmaParams.srcAddr = inIntNewVideoCurrent;

        dmaParams.dstAddr = outExtVideo;

        ACPY3_configure(inst->dmaHandles[1], &dmaParams, 0);

        ACPY3_start(inst->dmaHandles[1]);

        ACPY3_wait(inst->dmaHandles[1]);

        outExtVideo += 1280;

    }

    ACPY3_deactivate(inst->dmaHandles[0]);

    ACPY3_deactivate(inst->dmaHandles[1]);

As long as pointer in red (inIntNewVideoCurrent) is allocated from DDR3 it works fine. If inIntNewVideoCurrent is allocated from scratch buffer [L2 or L1 RAM] (via IALG_MemRec memTab[]), nothing gets written into the outExtVideo pointer. DSKT2 INT_HEAP buffers aren't accessible via DMA. Using "memcpy", on the other hand works.

 RV

Can you share your cfg file with me ? I'd like to compare it with mine. 

I want to take a look at how the heaps are created and assigned to DSKT2.

DMA via ACPY3/DMAN3 works only between to DDR3 locations.

Here it is ( I am only including relevant parts):

 

/*

 *  ======== bios6.cfg ========

 *  Common configuration for setting up BIOS 6 configuration.

 */

var Platform = Program.platformName;

var DeviceName = Program.cpu.deviceName;

var CpuCore = Program.cpu.attrs.cpuCore;

function getInternalHeapName() {

    if ((Platform.match(/DM8168/)) || (Platform.match(/DM8148/)) ||

        (Platform.match(/TI816X/))) {

        if (CpuCore == "CM3") {

            /*

             * We don't want to use internal memory for Ducati-based chips

             * since the platform's internal memory base address is virtual,

             * which means that we would also need to setup the AMMU to be

             * able to address it.

             */

            return("DDR3_M3");

        } else if (CpuCore == "674") {

            return("IRAM");

        }

    }

    else if (Platform.match(/evm6472/)) {

        return("LL2RAM");

    }

    else if (Platform.match(/evm6474/)) {

        return("L2RAM");

    }

    else if (Platform.match(/DA830|3430|3530/)) {

        return("IRAM");

    }

    else if ((Platform.match(/simTesla/)) || (Platform.match(/sdp4430/))) {

        if (CpuCore == "64T") {

            return("L2SRAM");

        } else if (CpuCore == "CM3") {

            /* M3 */

            return("L2_RAM");

        }

    }

    else if (Platform.match(/6467/)) {

        return("IRAM");

    }

    else if (Platform.match(/6616|6608|6670|6678/)) {

        return("L2SRAM");

    }

    else {

        /* everything else */

        return("IRAM");

    }

}

function getExternalHeapName() {

    if ((Platform.match(/simTesla/)) || (Platform.match(/sdp4430/))) {

        return("EXT_RAM");

    }

    else if (Platform.match(/sdp2430/)) {

        return("DDR");

    }

    else if (Platform.match(/DA830|sdp3430/)) {

        return("SDRAM");

    }

    else if (Platform.match(/TI816X/) || Platform.match(/DM8148/)) {

        if (CpuCore == "CM3") {

            return("DDR3_M3");

        } else if (CpuCore == "674") {

            return("DDR3_DSP");

        }

    }

    else if (Platform.match(/6616|6608|6670|6678/)) {

        return("DDR3");

    }

    else {

        /* everything else */

        return("DDR2");

    }

}

function createHeapMem(size, sectionName, heapName) {

    var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');

    var heapMemParams = new HeapMem.Params();

    heapMemParams.size = size;

    heapMemParams.sectionName = sectionName;

    Program.sectMap[sectionName] = heapName;

    return HeapMem.create(heapMemParams);

}

 

*  ======== heaps.cfg ========

 */

var platformName = Program.platformName;

print("platformName = '" + platformName + "'");

var platform = Program.platform;

var heapConfig = xdc.loadCapsule('ti/sdo/ce/examples/buildutils/heap_config.cfg');

// consider platform-based files, checkout Rams & Gunjan approaches

// table-based?

var internalMemoryName = heapConfig.getInternalHeapName();

var internalHeapSize = 0xc000;     //  48 kB

var externalMemoryName = heapConfig.getExternalHeapName();

var externalHeapSize = 0x20000;    // 128 kB

/* Configure internal and external heaps */

Program.global.EXT_HEAP =

    heapConfig.createHeapMem(externalHeapSize, ".EXT_HEAP", externalMemoryName);

Program.global.INT_HEAP =

    heapConfig.createHeapMem(internalHeapSize, ".INT_HEAP", internalMemoryName);

if (!platformName.match(/evm6472|evm6474|6608|6616|6670|6678/)) {

    /* This is a SysLink-based system, create a DDRALGHEAP section */

    var DDRALGMemoryName = "DDRALGHEAP";

    var DDRALGHeapSize = platform.externalMemoryMap[DDRALGMemoryName].len;

    Program.global.EXTALG_HEAP = heapConfig.createHeapMem(DDRALGHeapSize, ".EXTALG_HEAP", DDRALGMemoryName);

}

/* Place code */

Program.sectMap[".text"]      = externalMemoryName;

/* Set the default heap to the external heap */

var Memory = xdc.useModule('xdc.runtime.Memory');

Memory.defaultHeapInstance = Program.global.EXT_HEAP;

 *  ======== all_syslink.cfg ========

 *

 *  For details about the packages and configuration parameters used throughout

 *  this config script, see the Codec Engine Configuration Guide (link

 *  provided in the release notes).

 */

xdc.loadCapsule('./heaps.cfg');

/* Setup xdcruntime proxys */

xdc.useModule('ti.sysbios.xdcruntime.Settings');

var platformName = Program.platformName;

var osalGlobal = xdc.useModule('ti.sdo.ce.osal.Global');

/* SysLink-based slave server */

osalGlobal.runtimeEnv = osalGlobal.DSPLINK_BIOS;

/* IPC-related config */

xdc.useModule('ti.sdo.ce.ipc.dsplink.dsp.Settings');

var MultiProc = xdc.useModule('ti.sdo.utils.MultiProc');

var myName;

// put into platform capsule

if (platformName.match(/DM8168/) || platformName.match(/DM8148/) ||

    platformName.match(/TI816X/)) {

    if (platformName.match(/:VIDEO-M3/)) {

        var Core = xdc.useModule('ti.sysbios.family.arm.ducati.Core');

        Core.id = 0;

        myName = "VIDEO-M3";

    }

    else if (platformName.match(/:VPSS-M3/)) {

        var Core = xdc.useModule('ti.sysbios.family.arm.ducati.Core');

        Core.id = 1;

        myName = "VPSS-M3";

    }

    else {

        myName = "DSP";

    }

} else {

    myName = "DSP";

}

var settings = xdc.useModule('ti.sdo.ipc.family.Settings');

var procNames = settings.getDeviceProcNames();

MultiProc.setConfig(myName, procNames);

var platformBaseName = platformName.replace(/(\w+)\:.*$/, "$1").replace(/\./g, "_");

try {

    xdc.loadCapsule(platformBaseName + ".cfg");

} catch(e) {

    throw "Error: cannot load example's platform capsule '" + platformBaseName + ".cfg' (either it doesn't exist or there's an error inside it)";

}

/* TODO:L need to add UIA Log collection support */

//xdc.useModule('ti.sdo.ce.bioslog.LogServer');

/* to link in release libs, remove the following lines */

xdc.useModule('ti.sdo.ce.global.Settings').profile = "debug";

xdc.useModule('ti.sdo.fc.global.Settings').profile = "debug";

/*

 *  ======== Server Configuration ========

 */

var Server = xdc.useModule('ti.sdo.ce.Server');

/* The server's stackSize.  More than we need... but safe. */

Server.threadAttrs.stackSize = 4096;

/* The servers execution priority */

Server.threadAttrs.priority = Server.MINPRI;

Server.stackSizePad = 9000;

var DSKT2 = xdc.useModule('ti.sdo.fc.dskt2.DSKT2');

DSKT2.DARAM0 = "INT_HEAP";

DSKT2.DARAM1 = "INT_HEAP";

DSKT2.DARAM2 = "INT_HEAP";

DSKT2.SARAM0 = "INT_HEAP";

DSKT2.SARAM1 = "INT_HEAP";

DSKT2.SARAM2 = "INT_HEAP";

DSKT2.ESDATA = "EXTALG_HEAP";

DSKT2.EPROG = "EXTALG_HEAP";

DSKT2.IPROG = "INT_HEAP";

DSKT2.DSKT2_HEAP = "EXT_HEAP";

DSKT2.ALLOW_EXTERNAL_SCRATCH = false;

DSKT2.SARAM_SCRATCH_SIZES[0] = 32 * 1024;  // 32k scratch for groupId 0

var TMS320TI816X = xdc.useModule('ti.catalog.c6000.TMS320TI816X');

/* M3's currently don't support DMAN3 */

if (!(Program.build.target.isa.match(/^v7M$/))) {

/*

 *  ======== DMAN3 (DMA manager) configuration ========

 */

var DMAN3 = xdc.useModule('ti.sdo.fc.dman3.DMAN3');

DMAN3.heapInternal    = "INT_HEAP";

DMAN3.heapExternal    = "EXTALG_HEAP";

DMAN3.idma3Internal   = false;

DMAN3.scratchAllocFxn = "DSKT2_allocScratch";

DMAN3.scratchFreeFxn  = "DSKT2_freeScratch";

        DMAN3.maxPaRamEntries = 512;

DMAN3.paRamBaseIndex     = 129;  // Since all Params above 128 are available for DSP, let's make it simple and start from there.

DMAN3.numPaRamEntries    = 48;  // number of PaRAM sets exclusively usedby DMAN, application dependent

DMAN3.nullPaRamIndex = 128;  //By default, PaRam 0 is used, but often QDMA channels by default are mapped to PaRam 0, so lets switch to something safer.

DMAN3.numQdmaChannels    = 6;   // number of device's QDMA channels to use

DMAN3.qdmaChannels       = [2,3,4,5,6,7]; // QDMA channels 2-7 are available for use

DMAN3.tccAllocationMaskL = 0xFC00000F;   // bit mask indicating which TCCs 0..31 are available for use, created using above table.

DMAN3.tccAllocationMaskH = 0xFF0F0000; // bit mask indicating which TCCs 32..63 are available for use, created using above table.

DMAN3.numPaRamGroup[0]   = 48;  //number of PaRAM sets for scratch group 0, application dependent number.

DMAN3.numTccGroup[0]     = 22;  //number of TCCs assigned to scratch group 0, application dependent BUT reducing this to 22 since that is the maximum number

  //of TCCs available to DSP per table above.

} // !M3

/*

 *  ======== RMAN (IRES Resource manager) configuration ========

 */

/* TODO: What all do I set up here from RMANs perspective ?

         Should this be here or in OSAL? */

var RMAN = xdc.useModule('ti.sdo.fc.rman.RMAN');

RMAN.useDSKT2 = true;

RMAN.tableSize = 10;

// Set up logging

xdc.loadCapsule('ti/sdo/ce/examples/buildutils/server_log.cfg');

RV

 

Hello,

Gunjan

I am now facing similar problems on dm8168. Could you help solve the problem?

Problem pasts here

http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/268526.aspx

Regards,

Yang

Hello Yang,

If your problem is described on the post linked above, could you please follow Janet's instructions and share the entire log ? As she mentioned it looks like your memory allocation has failed.

It does not seem related to this post above. This post has to do with a DMA transfer in internal memory not completing properly. Please clarify the exact issue you need help with.

Thanks,

Gunjan

Hi,

Gunjan

Thanks for your reply.

The problem I am facing is memory allocation in L2 cache.

The log message has been pasted.

And I have not solved the problem yet.

Hope for your help.

Regards,

Yang