SPI DMA timing

Hi

I'm using the Logic EVM with C6748 SOM and I'm investigating spi transfer. So far, I have spi working in dma mode. However, like a few others  on this forum, I've noticed that there is quite a big delay between chip select and start of spi clock if CSHOLD is set. This delay is not present if CSHOLD is not set. Here are two screenshots to illustrate this. Note that I did not specify any delays (wDelay, c2TDelay and t2Cdelay are all 0).

If CSHOLD is not set:

If CSHOLD is set:

Note that there suddenly is 52.9 us delay between CS going low and the start of clock, and 39.5 us between stopping the clock and CS going high. This is a lot compared to the 2.2 us it takes to actually transfer the two bytes in this experiment.

To track this delay down, I've started hacking the spi edma driver (Spi_edma.c) and inserting gpio low/high transitions on some critical points in Spi_localEdmaTransfer(). What I've noticed is:

1. if CSHOLD is not set, the spi transfer seems faster, but is in fact not. There is no (or hardly any) delay between CS going low (/high) at the start (/end) of the clock, but there is approximally 48 us delay between entering Spi_localEdmaTransfer() and actually pulling CS low and again a delay between pulling CS high and leaving this function.
2. most of the delays are caused by the EDMA3 function calls: EDMA3_DRV_getPaRAM() consumes 10 - 13 us, EDMA3_DRV_setPaRAM() consumes 8 - 10 us and EDMA3_DRV_enableTransfer() consumes 2 - 5 us. Since all those functions are called twice (once for transmit and once for receive), this is a penalty of ~ 46 us (oddly enough, the second time these functions are called, they are typically faster than the first time).

I have not investigated why the EDMA3 calls take such a relatively long time (that would be just a little too much in depth for today). I did however hack the spi driver and extended the Spi_DataParam struct with a Uint8 skipConfig field. I also replaced the paramSet struct in Spi_localEdmaTransfer() with two static structs paramRxSet and paramTxSet. With a little more logic in Spi_localEdmaTransfer(), it now skips the EDMA3_DRV_getPaRAM() calls if skipConfig is set to 1. This results in the following timings:

CSHOLD is set:

The CS low to start of clock delay is now 32 us, so approximally 40% faster than before.

I have not investigated the delay between the end of clock and CS high since I do not know where this time is spent.

The main questions I have now are:

1. Are these delays in EDMA3_DRV_* function calls normal?
2. And are there any methods to reduce these delays?

Thanks in advance.

Admar

PS: For the record: I have the Logic EVM with C6748 SOM, psp drivers 01_30_00_05, BIOS 5.41.09.34 and edma3_lld_01_10_00_01 (at least, I think it is using that one).