Because of the Thanksgiving holiday in the U.S., TI E2E™ design support forum responses may be delayed from November 25 through December 2. Thank you for your patience.

  • State Resolved
  • Locked Locked
  • Replies 5 replies
  • Subscribers 101 subscribers
  • Views 3718 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Timing DDR DM368 MT47H64M16HR-25E IT:H

Maxime Suire
Prodigy 250 points

Hi,

I am currently developing a board with the DM368 and RAM MT47H64M16HR-25E IT:H. I use a copy of the SD Card DM368 EVM SDK where there is 3 partitions (BOOT START_HERE ROOTFS). The uboot and linuxSDK are in the SD CARD .

This is what happen on boot:

 


DM36x initialization passed!
TI UBL Version: 1.50
Booting Catalog Boot Loader
BootMode = SD/MMC
Starting SDMMC Copy...
   DONE
Jumping to entry point at 0x81080000.


U-Boot 2010.12-rc2 (Mar 24 2011 - 16:49:26)

Cores: ARM 432 MHz
DDR:   340 MHz
I2C:   ready
DRAM:  128 MiB
NAND:  nand_get_flash_type: unknown NAND device: Manufacturer ID: 0x2c, Chip ID: 0x48
No NAND device found!!!
0 MiB
MMC:   davinci: 0, davinci: 1
*** Warning - readenv() failed, using default environment

Net:   Read from EEPROM @ 0x50 failed
Ethernet PHY: GENERIC @ 0x00
DaVinci-EMAC
Hit any key to stop autoboot:  0
reading boot.scr

388 bytes read
## Executing script at 80600000
reading uImage

2148136 bytes read
## Booting kernel from Legacy Image at 80700000 ...
   Image Name:   Arago/2.6.32.17-psp03.01.01.39/d
   Created:      2011-03-24  21:31:41 UTC
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    2148072 Bytes = 2 MiB
   Load Address: 80008000
   Entry Point:  80008000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK
OK

Starting kernel ...

Uncompressing Linux............................................................................................................................................ done, booting th.



There is a problem of timing DDR.
I should modify the file : /home/user/ti-dvsdk_dm368-evm_4_02_00_06/psp/flash-utils/DM36x/Common/device.c


But I don't know what are the differents values for:

static const Uint16 DDR_T_RFC = 1275;
static const Uint16 DDR_T_RP = 200;
static const Uint16 DDR_T_RCD = 200;
static const Uint16 DDR_T_WR = 150 ;
static const Uint16 DDR_T_RAS = 450;
static const Uint16 DDR_T_RC = 650;
static const Uint16 DDR_T_RRD = 100;
static const Uint16 DDR_T_WTR = 100;
static const Uint32 DDR_T_RASMAX = 700000;
static const Uint16 DDR_T_XP = 2;
static const Uint16 DDR_T_XSNR = 1375;
static const Uint16 DDR_T_XSRD = 199;
static const Uint16 DDR_T_RTP = 75;
static const Uint16 DDR_T_CKE = 3;
static const Uint16 DDR_RR = 78;

???


What are the differents values for MT47H64M16HR-25E IT:H ?

Regards

    Maxime SUIRE

 

  • 0
    TI__Genius 16130 points

    Maxime,

    You need to derive these values from the AC timings values from the DDR2 datasheet and the DDR2 clock frequency you are using.

    You can get the idea of what is going on from this page http://processors.wiki.ti.com/index.php/Setting_up_AM35x_SDRC_registers. We do not have an equivalent page for the DM368 but it will give you most, if not all, of the data you need as the DDR controllers will be very similar.

    Iain 

  • 0 in reply to Iain Hunter
    Prodigy 250 points

    Hi,

    Thanks for your reply.

     

    Here the new parameters:

    static const Uint16 DDR_T_RFC = 1275;
    static const Uint16 DDR_T_RP = 125;
    static const Uint16 DDR_T_RCD = 125;
    static const Uint16 DDR_T_WR = 150 ;
    static const Uint16 DDR_T_RAS = 400;
    static const Uint16 DDR_T_RC = 550;
    static const Uint16 DDR_T_RRD = 100;
    static const Uint16 DDR_T_WTR = 75;
    static const Uint32 DDR_T_RASMAX = 700000;
    static const Uint16 DDR_T_XP = 2;
    static const Uint16 DDR_T_XSNR = 1375;
    static const Uint16 DDR_T_XSRD = 200;
    static const Uint16 DDR_T_RTP = 75;
    static const Uint16 DDR_T_CKE = 3;
    static const Uint16 DDR_RR = 78;

     

    Is there an other thing to change ?

    Traduire du texte ou une page Web
    should I change?



      DDR->SDTIMR =    tRFC << 25  |

                       tRP  << 22  |

                       tRCD << 19  |

                       tWR  << 16  |

                       tRAS << 11  |

                       tRC  << 6   |

                       tRRD << 3   |

                       tWTR << 0;



       DDR->SDTIMR2 =  ((DDR_T_RASMAX / (DDR_RR * DDR_FREQ)) << 27) |

                       (DDR_T_XP << 25 )    |

                       (((DDR_T_XSNR * DDR_FREQ) / 10000) << 16)   |

                       (DDR_T_XSRD << 8)    |

                       (((DDR_T_RTP * DDR_FREQ) / 10000) << 5)  |

                        (DDR_T_CKE << 0);



           DDR->SDBCR = 0x534832; //0x534832; Reset the TIMUNLOCK TMR Write Disable



           DDR->PBBPR = 0x000000FE;



           DDR->SDBCR = 0xD34A32;   //Enable DDR2 and DDR and SDram. Write '1' to
    BOOTUNLOCK



           DDR->SDBCR = 0x534A32;  //Enable DDR2 and DDR and SDram. Write '0' to BOOTUNLOCK



           DDR->SDRCR = (DDR_RR * DDR_FREQ) / 10; //Program SDRAM Refresh
    Control Registers

    Regards

     

    Maxime SUIRE

  • 0 in reply to Maxime Suire
    Prodigy 250 points

    Hi,

    Thanks for your reply.

     

    Here the new parameters:

    static const Uint16 DDR_T_RFC = 1275;
    static const Uint16 DDR_T_RP = 125;
    static const Uint16 DDR_T_RCD = 125;
    static const Uint16 DDR_T_WR = 150 ;
    static const Uint16 DDR_T_RAS = 400;
    static const Uint16 DDR_T_RC = 550;
    static const Uint16 DDR_T_RRD = 100;
    static const Uint16 DDR_T_WTR = 75;
    static const Uint32 DDR_T_RASMAX = 700000;
    static const Uint16 DDR_T_XP = 2;
    static const Uint16 DDR_T_XSNR = 1375;
    static const Uint16 DDR_T_XSRD = 200;
    static const Uint16 DDR_T_RTP = 75;
    static const Uint16 DDR_T_CKE = 3;
    static const Uint16 DDR_RR = 78;

     

    Is there an other thing to change ?

    should I change?



      DDR->SDTIMR =    tRFC << 25  |

                       tRP  << 22  |

                       tRCD << 19  |

                       tWR  << 16  |

                       tRAS << 11  |

                       tRC  << 6   |

                       tRRD << 3   |

                       tWTR << 0;



       DDR->SDTIMR2 =  ((DDR_T_RASMAX / (DDR_RR * DDR_FREQ)) << 27) |

                       (DDR_T_XP << 25 )    |

                       (((DDR_T_XSNR * DDR_FREQ) / 10000) << 16)   |

                       (DDR_T_XSRD << 8)    |

                       (((DDR_T_RTP * DDR_FREQ) / 10000) << 5)  |

                        (DDR_T_CKE << 0);



           DDR->SDBCR = 0x534832; //0x534832; Reset the TIMUNLOCK TMR Write Disable



           DDR->PBBPR = 0x000000FE;



           DDR->SDBCR = 0xD34A32;   //Enable DDR2 and DDR and SDram. Write '1' to
    BOOTUNLOCK



           DDR->SDBCR = 0x534A32;  //Enable DDR2 and DDR and SDram. Write '0' to BOOTUNLOCK



           DDR->SDRCR = (DDR_RR * DDR_FREQ) / 10; //Program SDRAM Refresh
    Control Registers

    Regards

     

    Maxime SUIRE

  • 0 in reply to Maxime Suire
    TI__Genius 16130 points

    Maxime,

    You will also need to review any other changes you have made between your board and the TI EVM that may affect UBL code.

    My suggestion would be that you use CCS to load the UBL code to RAM and then step through it and use CCS's memory window to check that your DDR2 interface is correctly set up and that you can read/write DDR2. This is much easier than trying to guess where a problem is if UBL fails to execute and load Uboot properly.

    Iain 

  • 0 in reply to Iain Hunter
    Prodigy 250 points

    Iauin,

    Thanks for your reply.

    I don't wan't to use CCS. Did my suggestions for the variables T_DDR seems correct.

    I have to change register  for the PLL?

    #define PLL1_MUL        0x51
    #define PLL1_PREDIV        0x7
    #define PLL1_POSTDIV    0x0         //PVCO will 24*2M/N+1 = 486 Mhz
     
    #define PLL1_DIV1        0x13    //POST DIV 486/20=24.3 Mhz->USB PHY  
    #define PLL1_DIV2        0x1    //POST DIV 486/2=243Mhz->ARM926/ARM968
    #define PLL1_DIV3        0x1    // POST DIV 486/2 = 243 Mhz  -> MJCP/HDVICP
    #define PLL1_DIV4        0x3    // POST DIV 486/4 = 121.5 Mhz  -> EDMA/Peripheral CFG0 (1/2 Kaleido clock)
    #define PLL1_DIV5        0x1    // POST DIV 486/2 = 243Mhz -> VPSS (max 270)
    #define PLL1_DIV6        0x11    // POST DIV 486/18 = 27 Mhz -> VENC    
    #define PLL1_DIV7        0x0    // POST DIV 486/1 = 486Mhz -> DDRx2
    #define PLL1_DIV8        0x4    // POST DIV 486/5 = 97.25Mhz-> MMC0/SD0
    #define PLL1_DIV9        0x1    // POST DIV 486/2 = 24.3Mhz-> CLKOUT  
     
     
    #define PLL2_MUL        0x63
    #define PLL2_PREDIV        0x7
    #define PLL2_POSTDIV    0x0         //PLL2 Output (0x63 * 2 * 24 / (0x7 + 1) = 594MHZ
     
    #define PLL2_DIV1        0x18    // 594/25 23.6 MHZ USB
    #define PLL2_DIV2        0x1      // 594/2 =297 Mhz -> ARM  
    #define PLL2_DIV3        0X1        // 297 MHZ 2 * ddr
    #define PLL2_DIV4        0x1c     // POST DIV 594/29 = 20.48 -> VOICE
    #define PLL2_DIV5        0x07     // POST DIV 594/8 = 74.25 ->VIDEO HD
     
    #define PERIPHERAL_CLK_CTRL_VAL    0x243F04FC
     
    #define DDR_FREQ         400  //243

    Regards

    Maxime Suire