I am trying to use IPC to send messages from ARM to a DSP core on a 6638 emv. I am using: IPC_3_00_00_20 CCS 5.4 XTCIEVMK2X
On the DSP side I use the .cfg
MultiProc.setConfig(null, ["HOST", "CORE0"]); Ipc.procSync = Ipc.ProcSync_PAIR; MultiProc.numProcessors = 2; var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion'); SharedRegion.setEntryMeta(0, { base: SHAREDMEM, len: 0x00200000, ownerProcId: 1, isValid: true, name: "MSMCSRAM_IPC", });
On the ARM side I am running Linux and using the MessageQ example
The DSP gets to a loop for Ipc_attach() which returns Ipc_E_NOTREADY as expected. On the ARM side the Ipc_start() fails.
On the ARM side I get the message: Ipc_start: NameServer_setup() failed: -1
In this scenario I have simplified the intention to only setup communication between the ARM and CORE0 only.
Debugging into ARM code I see that there is an assumption upfront that there are 9 processors and ordered as HOST,CORE0,CORE1... The IPC users guoide starngely is titled "SYS/BIOS IPC" not explaining the Linux issues and details.
Question 1: Where does the ARM get the information about the configuration from? How does it know which CORE it should connect to? how is the equivalen information in .cfg for dsp is given to ARM? That is How would I run Ipc_attach() from MessageQ example on ARM, whithout being able to convey an equivalent "Ipc.procSync = Ipc.ProcSync_PAIR;" concept to ARM?
Note; debugging into ARM side I see Client_Info[0] has been initialized to PID=1650 responseFIFOName[]=/tmp/LAD/1650 and Client_Info[1..31] are all null. In one occation stepping through the ARM side and stepping into ant call possible i got further than ever and the app terminated with: qTStatus: Remote communication error. Target disconnected.: Connection reset by peer.
If I setp through (by stepping over Ipc_start()) I will get: Ipc_start: NameServer_setup() failed: -1
Question 2: On the ARM side before running the Ipc_start() calling MultiProc_getNumProcessors(), MultiProc_getId("CORE0"), MultiProc_self(), MultiProc_getId("HOST") returns: Number of processors = 0 , CORE0 id= 65536 , This core id=0 , HOST id = 65536
on the DSP CORE0; Number of processors=2 , CORE0 id=1 , this core id=0 ,HOST id=0 , name of id 0 is: HOST Note the "this core id=0" using MultiProc_self() is not what I expected!
I start the DSP by loading from CCS/JTAG and run th DSP and it gets to Ipc_attach() loop. Then I let the ARM run the app and step through the MessageQ code.
I have been able to program all dsp cores to communicate with MessageQ in 2,3,8 core configurations.