h264fhdvenc 01_10_02_06 encode 1080p abnormal

Sephrioth

Hi,

When I use this codec to encode 1080P, the X64P is generated successfully, but when I use it to encode, the result is: the I frame is good, but the size is a little large, but P frame size is 12 byte, such as in 30 frames, ths size is (108290, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12).

My environment is :

    DM6467
    DVSDK 2_00_00_22
    codec_engine_2_26_02_11
    xdais_6_26_01_03
    bios_5_41_13_42
    HDVICP version 1.01.020

The code server config file encode.cfg:

/* set up OSAL */
var osalGlobal = xdc.useModule('ti.sdo.ce.osal.Global');
osalGlobal.runtimeEnv = osalGlobal.DSPLINK_BIOS;

/* configure default memory seg id to BIOS-defined "DDR" */
osalGlobal.defaultMemSegId = "DDR2";

/* Initialize trace buffer size */
osalGlobal.traceBufferSize = 0x40000;

/* Enable DSP-side BIOS logging */
var LogServer = xdc.useModule('ti.sdo.ce.bioslog.LogServer');

/*
* ======== Server Configuration ========
*/
var Server = xdc.useModule('ti.sdo.ce.Server');
Server.threadAttrs.stackSize = 16384;

/* get various codec modules; i.e., implementation of codecs */
var H264ENC = xdc.useModule('ti.sdo.codecs.h264enc.ce.H264ENC')
var H264FHDVENC = xdc.useModule('ti.sdo.codecs.h264fhdvenc.ce.H264FHDVENC');
var AACHEENC = xdc.useModule('ti.sdo.codecs.aacheenc.ce.AACHEENC');
var G711ENC = xdc.useModule('ti.sdo.codecs.g711enc.ce.G711ENC');

/* Linking in the HDVICP Lib module */
xdc.useModule('ti.sdo.codecs.hdvicp.HDVICP');

if (prog.build.cfgArgs.profile == "eval") {
    /* This server is for evaluation, so use the watermarked versions */
    print("Configuring server to use watermarked codecs...");
    H264ENC.alg.watermark = true;
    H264FHDVENC.alg.watermark = true;
    AACHEENC.alg.watermark = true;
    G711ENC.alg.watermark = true;

}
else
{
/* This server is for production, so use the actual versions */
    print("Configuring server to use original codecs...");
   H264ENC.alg.watermark = false;
    H264FHDVENC.alg.watermark = false;
    AACHEENC.alg.watermark = false;
    G711ENC.alg.watermark = false;
}

H264ENC.alg.codeSection = "DDR2";
H264ENC.alg.udataSection = "DDR2";
H264ENC.alg.dataSection = "DDR2";

H264FHDVENC.alg.codeSection = "DDR2";
//H264FHDVENC.alg.intMemSection = "IRAM";

H264FHDVENC.alg.udataSection = "DDR2";
H264FHDVENC.alg.dataSection = "DDR2";

/* Switching off Outs Bufs Cache */
H264ENC.manageInBufsCache = [true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true];
H264ENC.manageOutBufsCache = [true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true];
//H264ENC.manageOutBufsCache = [ false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false ];
H264FHDVENC.manageInBufsCache = [true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true];
H264FHDVENC.manageOutBufsCache = [true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true];

Server.algs = [
   {name: "h264enc", mod: H264ENC,groupId:0,threadAttrs: {
        stackMemId: 0, priority: Server.MINPRI + 1}
    },
    {name: "h264fhdvenc", mod: H264FHDVENC,groupId:0,threadAttrs: {
            stackMemId: 0, priority: Server.MINPRI + 1}
    },
   {name: "aacheenc", mod: AACHEENC,groupId:1,threadAttrs: {
            stackMemId: 0, priority: Server.MINPRI + 2}
    },
   {name: "g711enc", mod: G711ENC,groupId:1,threadAttrs: {
            stackMemId: 0, priority: Server.MINPRI + 2}
    },
];

   /*
    * ======== DSKT2 and RMAN Configuration ========
    * XDAIS Algorithm Memory and DMA allocation
    */

    var DSKT2 = xdc.useModule('ti.sdo.fc.dskt2.DSKT2');
    DSKT2.DARAM0     = "IRAM";
    DSKT2.DARAM1     = "IRAM";
    DSKT2.DARAM2     = "IRAM";
    DSKT2.SARAM0     = "IRAM";
    DSKT2.SARAM1     = "IRAM";
    DSKT2.SARAM2     = "IRAM";
    DSKT2.ESDATA     = "DDRALGHEAP";
    DSKT2.IPROG      = "IRAM";
    DSKT2.EPROG      = "DDR2";
    DSKT2.DSKT2_HEAP = "DDR2";    /* to allocate internal DSKT2 object */

    /* Scratch group 0 */
    DSKT2.DARAM_SCRATCH_SIZES[0] = 65536;
    DSKT2.SARAM_SCRATCH_SIZES[0] = 65536;

    /* Scratch group 1 */
    DSKT2.DARAM_SCRATCH_SIZES[1] = 0;
    DSKT2.SARAM_SCRATCH_SIZES[1] = 0;

    var RMAN = xdc.useModule('ti.sdo.fc.rman.RMAN');
    RMAN.useDSKT2 = true;
    RMAN.tableSize = 10;
    RMAN.semCreateFxn = "Sem_create";
    RMAN.semDeleteFxn = "Sem_delete";
    RMAN.semPendFxn = "Sem_pend";
    RMAN.semPostFxn = "Sem_post";

    var EDMA3 = xdc.useModule('ti.sdo.fc.edma3.Settings');
    EDMA3.maxPaRams[0] = 384;
    EDMA3.maxTccs[0] = 49;
   EDMA3.maxTccs[1] = 0;
    EDMA3.maxEdmaChannels[0] = 49;
   /*
   EDMA3.maxEdmaChannels[1] = 0;
   EDMA3.maxQdmaChannels[0] = 0;
   */
   EDMA3.maxQdmaChannels[0] = 4;
   EDMA3.maxQdmaChannels[1] = 0;
    EDMA3.regionConfig = "DM6467_Config";

    var EDMA3CHAN = xdc.useModule('ti.sdo.fc.ires.edma3chan.EDMA3CHAN');
    var HDVICP = xdc.useModule('ti.sdo.fc.ires.hdvicp.HDVICP');

    var HDINTC = xdc.useModule('ti.sdo.fc.hdintc.HDINTC');
    HDINTC.interruptVectorId_0 = 10;
    HDINTC.interruptVectorId_1 = 11;
    HDINTC.hdvicpInterruptEventNo_0 = 29;
    HDINTC.hdvicpInterruptEventNo_1 = 39;

    HDINTC.biosInterruptVectorId_0 = 7;
    HDINTC.biosInterruptVectorId_1 = 8;
    HDINTC.biosInterruptEventNo_0 = 30;
    HDINTC.biosInterruptEventNo_1 = 31;

The encode.tcf is:

    /*
* Setup platform-specific memory map, CLK rate, etc.
*/
var mem_ext = [
    // will use for cmem: base: 0x87800000 (120MB offset), size: 0x04200000 (66MB)
{
    comment:    "DDRALGHEAP: off-chip memory for dynamic algmem allocation",
    name:       "DDRALGHEAP",
    base:       0x8BA00000,
    len:        0x04000000,   // 66MB
    space:      "code/data"
},
{
    comment:    "DDR2: off-chip memory for code and data",
    name:       "DDR2",
    base:       0x8FA00000,   // 250MB offset
    len:        0x00400000,   // 4MB size
    space:      "code/data"
},
{
    comment:    "DSPLINK: off-chip memory for DSPLINK code and data",
    name:       "DSPLINKMEM",
    base:       0x8FE00000,   // 254MB
    len:        0x00100000,   //   1MB
    space:      "code/data"
},
{
    comment:    "RESET_VECTOR: off-chip memory for the reset vector table",
    name:       "RESET_VECTOR",
    base:       0x8FF00000,
    len:        0x00000080,
    space:      "code/data"
},
];

/* Specify the L2 memory setting */
var device_regs = {
    l1PMode: "32k",
    l1DMode: "32k",
    //l2Mode: "32k"
    l2Mode: "64k"
};

var params = {
    clockRate: 594,
    catalogName: "ti.catalog.c6000",
    deviceName: "DM6467",
    regs: device_regs,
    mem: mem_ext
};

/*
* Customize generic platform with parameters specified above.
*/
utils.loadPlatform("ti.platforms.generic", params);

/* ===========================================================================
* Enable heaps and tasks
* ===========================================================================
*/
bios.enableMemoryHeaps(prog);
bios.enableTskManager(prog);

/* ===========================================================================
* Create heaps in memory segments that are to have heap
* ===========================================================================
*/
bios.DDR2.createHeap = true;
bios.DDR2.heapSize   = 0x00040000; // 256K

bios.DDRALGHEAP.createHeap = true;
bios.DDRALGHEAP.heapSize   = bios.DDRALGHEAP.len;

/* ===========================================================================
* GBL
* ===========================================================================
*/
prog.module("GBL").ENABLEALLTRC    = false;
prog.module("GBL").PROCID          = 0;

/*
bios.MEM.instance("IRAM").base = 0x11818000;
bios.MEM.instance("IRAM").len = 0x18000;
bios.MEM.instance("CACHE_L2").base = 0x11818000+0x18000;
bios.MEM.instance("CACHE_L2").len = 0x8000;
*/

prog.module("GBL").C64PLUSCONFIGURE   = true ;
prog.module("GBL").C64PLUSMAR128to159 = 0x0000ffff;

/* ===========================================================================
* HWI
* ===========================================================================
*/
bios.HWI_INT4.interruptSelectNumber = 16
bios.HWI_INT5.interruptSelectNumber = 17

/* ===========================================================================
* MEM
* ===========================================================================
*/
prog.module("MEM").STACKSIZE = 0x1000 ;
prog.module("TSK").STACKSIZE = 0x1000 ;

/* ===========================================================================
* Global Settings
* ===========================================================================
*/
prog.module("MEM").ARGSSIZE = 200;

/* ===========================================================================
* Enable MSGQ and POOL Managers
* ===========================================================================
*/
bios.MSGQ.ENABLEMSGQ = true;
bios.POOL.ENABLEPOOL = true;

/* ===========================================================================
* Set all code and data sections to use DDR
* ===========================================================================
*/
bios.setMemCodeSections (prog, bios.DDR2) ;
bios.setMemDataNoHeapSections (prog, bios.DDR2) ;
bios.setMemDataHeapSections (prog, bios.DDRALGHEAP) ;

/* ===========================================================================
* MEM : Global
* ===========================================================================
*/
prog.module("MEM").BIOSOBJSEG = bios.DDRALGHEAP;
prog.module("MEM").MALLOCSEG = bios.DDRALGHEAP;

/* ===========================================================================
* TSK : Global
* ===========================================================================
*/
prog.module("TSK").STACKSEG = bios.DDRALGHEAP ;

bios.TSK.instance("TSK_idle").stackSize = 0x1000;

//Fix for clock
prog.module("CLK").SPECIFYRATE = true;
prog.module("CLK").INPUTCLK = 148.5;

/* ===========================================================================
* Generate configuration files...
* ===========================================================================
*/
if (config.hasReportedError == false) {

bios.MEM.instance("IRAM").createHeap = 1;
//bios.MEM.instance("IRAM").heapSize = 0x18000;
bios.MEM.instance("IRAM").heapSize = 0x10000;   //64k
bios.MEM.instance("IRAM").enableHeapLabel = 1;
bios.MEM.instance("IRAM").heapLabel = prog.extern("IRAM_HEAP", "asm");
// !GRAPHICAL_CONFIG_TOOL_SCRIPT_INSERT_POINT!

    prog.gen();
}

what may cause such a situation.

Thanks.

over 13 years ago

0 Sephrioth over 13 years ago

Prodigy 110 points

The encode demo param is:

/*H264fhdenc Params*/
IH264FHDVENC_Params hd_params ={
       {
            sizeof(VIDENC1_Params),           /* size */
           XDM_DEFAULT,                      /* encodingPreset */
           IVIDEO_LOW_DELAY,                 /* rateControlPreset */
            1088,                              /* maxHeight */
           1920,                             /* maxWidth */
           30000,                            /* maxFrameRate */
           6000000,                          /* maxBitRate */
           XDM_LE_32,                         /* dataEndianness */
           0,                                /* maxInterFrameInterval */
           XDM_YUV_420SP,                     /* inputChromaFormat */
           IVIDEO_PROGRESSIVE,               /* inputContentType */
           XDM_CHROMA_NA
       },
       66,
       40,
       0
};

/* Use extended dynamic parameters to allow tweaking of the QP value */
IH264FHDVENC_DynamicParams extDynParams =
{
    {
        sizeof(IVIDENC1_DynamicParams),   /* size */
        1080,                              /* inputHeight */
        1920,                             /* inputWidth */
        30000,                            /* refFrameRate */
        30000,                            /* targetFrameRate */
        6000000,                          /* targetBitRate (override in app) */
        30,                               /* intraFrameInterval */
        XDM_ENCODE_AU,                    /* generateHeader */
        0,                                /* captureWidth */
        IVIDEO_NA_FRAME,                  /* forceFrame */
        0,                                /* interFrameInterval */
        0                                 /* mbDataFlag */
    },
#ifdef H241_MULTISLICE
       {IH264_SLICECODING_DEFAULT, IH264_SLICEMODE_BYTES, 1500, {0}, IH264_BYTE_STREAM},
#else
       {IH264_SLICECODING_DEFAULT, IH264_SLICEMODE_NONE, 0, {0}, IH264_BYTE_STREAM},
#endif
       -1, /* outBufSize */
       28, /* QPISlice */
       28, /* QPSlice */
       51, /* rateCtrlQpMax */
       0, /* rateCtrlQpMin*/
       0, /* numRowsInSlice */
       0, /* LfDisableIdc */
       0, /* LFAlphaC0Offset */
       0, /* LFBetaOffset */
       0, /* chromaQPOffset*/
       0, /* secChromaQPOffset */
       0, /* picAFFFlag */
       0, /* picOrderCountType */
       0, /* adaptiveMBs */
       0, /* SEIParametersFlag */
       0, /* VUIParametersFlag*/
       {0,0,}, /* VUIData */
       0, /* NALUnitCallback */
       1, /* skipStartCodesInCallback */ //changd from 0 to 1
       IH264FHDVENC_4x4_IP_FRAME, /* intra4x4EnableFlag */
       0, /* blockingCallFlag */
       1, /* MESelect */
       0, /* ME1080iMode */
       0, /* MVDataFlag */
       1, /* transform8x8DisableFlag*/
       IH264FHDVENC_8x8_NONE, /* Intra8x8EnableFlag */
       IH264FHDVENC_ONE_FIELD_DEFAULT, /* interlaceReferenceMode */
       IH264FHDVENC_CCV_LINEDROP, /* chromaConversionMode */
       1000, /* maxDelay */
       90, /* MaxSlicesSupported_IFrame */
       90, /* MaxSlicesSupported_PFrame */
};

0 Girish Srinivasa over 13 years ago in reply to Sephrioth

TI__Prodigy 480 points

Can you please check this?

http://e2e.ti.com/support/embedded/multimedia_software_codecs/f/356/p/51707/205796.aspx#205796

0 Sephrioth over 13 years ago in reply to Girish Srinivasa

Prodigy 110 points

Hi,Girish

Thank you for your reply, I have seen this post, the phenomenon is similar，but my h264fhdvenc version is 01_10_02_06 and in the codec server config file has been set

H264FHDVENC.alg.udataSection = "DDR2";

But the problem still is not resolved.

0 JIAXIN XU over 13 years ago in reply to Sephrioth

Prodigy 120 points

I have the same issue with u, when I use h264fhdvenc 01_10_02_03 and h264fhdvenc 01_10_02_05 , the encoded video stream is right, both P and I frame.but when I use h264fhdvenc 01_10_02_06 with the same parameters and encode demo, the encoded P frame is wrong

have you solved this issue yet? and how to solve?

could u give me some advice, please?

Thanks

0 Marc LEFORESTIER over 12 years ago in reply to Sephrioth

Prodigy 60 points

Hi,

You have put this thread as answered but I can't see what made your codec working.

I have the same trouble with 12 bytes P-Frame packets with the same h264fhvenc version.

Can you please tell me what is the workaround for this problem?

Thank you

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h264fhdvenc 01_10_02_06 encode 1080p abnormal