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Unable to read internal AM1806 registers with CCS

Thomas Mitchell
Intellectual 610 points
Other Parts Discussed in Thread: AM1806, SYSBIOS

When I build a SYS/BIOS project using a sample SYS/BIOS project (example using the SYS/BIOS mutex project) and I start the CCS debugger I can not read some of the internal hardware registers of the AM1806. Example: If I open the register window and select the PSC10ARM (PSC1 Register) the register window shows "Unable to read", but I can read other register just fine such as the PSC00ARM (PSC0 Register). There are other registers like the ARMINT, GPIO0 etc that I am also unable to read under CCS.

But if I build a small project that does not use SYS/BIOS all of the internal registers in the AM1806 are readable using the register window in CCS.

Both the SYS/BIOS project and the small project use the same GEL file and CCXML file.

Also in the SYS/BIOS project performing a write to one of the internal registers that CCS is unable to read causes an abort exception. In the small project that does not use SYS/BIOS the same instruction set works as expected and data is written to the register.

It looks like this register mapping is being done by something in the .CFG file [SYS/BIOS] but I can not find out what may be limiting access to these registers.

How can I set up SYS/BIOS so my code and CCS can access all the internal AM1806 registers?

Using CCS v 4.2.4 and SYS/BIOS v 6.32.5.54.

  • 0
    TI__Mastermind 30830 points

    Thomas,

    I think I understand the problem now.

    The issue is that to maximize performance, SYS/BIOS automatically configures and enables the ARM MMU and caches at startup.

    By default, only those memory regions identified in the platform and peripheral regions used by SYS/BIOS (ie timers and the interrupt controller) are made accessible to the processor.

    The peripheral regions you're trying to access are not being configured in the MMU.

    To add the peripherals you want to access to the MMU configuration you have to add MMU table entries in your config file.

    This can be done using the following as an example:

     var Cache = xdc.useModule('ti.sysbios.family.arm.arm9.Cache');
     var Mmu = xdc.useModule('ti.sysbios.family.arm.arm9.Mmu');

     // Enable the cache
     Cache.enableCache = true;

     // Enable the MMU (Required for L1 data caching)
     Mmu.enableMMU = true;

     // Force peripheral section to be NON cacheable
     var peripheralAttrs = {
         type : Mmu.FirstLevelDesc_SECTION, // SECTION descriptor
         bufferable : false,                // bufferable
         cacheable  : false,                // cacheable
     };

     // Define the base address of the 1 Meg page
     // the peripheral resides in.
     var peripheralBaseAddr = 0xa0400000;    /* substitute the 1MB base address of your peripheral here */

     // Configure the corresponding MMU page descriptor accordingly
     Mmu.setFirstLevelDescMeta(peripheralBaseAddr, peripheralBaseAddr, peripheralAttrs);

    You'll need to add an MMU page table entry for each unique 1MB page your peripherals belong to.

    Hope this helps.

    Alan