My customer is suffering from errors on the in the spare area on the flash so he tries to activate the ecc on the spare area. Here below is my customer question.
He uses AM3703 device with WINCE6.
During continues investigation I see that lot of the problem isn’t in an error correction method but it is in a corruption of the spare are.
If the spare area doesn’t covered by ECC, the invalid information about page will pass to the wear leveling part of the FSD. It means that storage may be destructed completely because the corruption the single page’s spare area.
I believe that the spare area’s guarding by ECC may solve the problem. How to do this?
Currently we use the wrapping mode 6 for read and mode 9 for write. It means that ECC engine is inactive during spare are read/write.
We must to choose the different wrapping mode to cover the spare area by ECC. (7 for write and 3 for read or something like)
Here we have some trebles.
Is it possible?
Can someone answer my customer's question?
We are not surethe scenario you are describing here is viable. In order to protect your spare area with ECC checking, you would have to store the ECC code of your spare area in a location different from the spare area for later comparison. Where do you plan on storing this ECC code?
To be honest we never got to the point where we would get spare area corruption hence never had to implement such an alogrithm. A better way would be to make sure you implement proper wear-leveling in your system to minimize potential risk of spare corruption.
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