Hi
Datasheet shows that RESET terminal must be asserted at power up.
(Q1)Is reset asserted timing at anytime in the following condition?
- After 3.3-V VCC reaches its 90%
- Before Enumeration
I am uneasy about interfering of USB enumeration by delay of TUSB2046B initialization.
(Q2) Could you tell me the time period of TUSB2046B initialization by reset terminal, please?
Best regards,
Shimizu