Hi,
For the two I2C bus traces, SCL and SDA, is there any requirement on their separation?
Even in fast I2C mode which runs at 400KHz, it is still much slower than DDR2 memory, USB and many other high-speed devices.
However, for DDR2, USB and SATA, there are specific requirements on routing including trace spacing, single-ended and differential impedance and so on; for I2C traces, is there any similar requirement?
In particular, per IPC 2221 standard Table 6-1, there are requirements on conductor spacing for in internal and external layers, and over different voltage ranges. For my application the voltage is below 5V, so the requirements are in the 1st row. For "Bare Board" ("Assembly" is about to assembly, soldering and conformal coating), even for external uncoated conductors a separation of 0.1mm = 4mil is enough. However, Table 6-1 assumes no particular context such as at which speed the signal is running, but is only about the minimum electrical clearance requirements.
For the case of I2C bus and assuming it is running at 400KHz fast mode, how much separation do I have to give between SCL and SDA traces? If I give very much, say, 20mil, then it is almost sure would work, but would waste PCB real estate, so I wish to know the minimum spacing at which I2C bus is guaranteed to work.
Could anyone help on this?
Tim