Dear Team,
I am a FAE in Serial Korea, in charge of All analog parts. ^^
I have one question about LVDS signal specification of SN65LVDS94(LVDS Receiver).
Customer : Digen (Application : AVN)
Question>
- Currently, as a result of measurement, Vp-p at CLK+ line is about 130mV. (Refer to the below image for this wave pattern.)
- Is it right? Is there any problem to receive the LVDS data through SN65LVDS94? (Customer wants to know what the minimum Vp-p of LVDS signal is.)
If you have any concern, please let me know it.
Thanks&Regards