problem with 74ls374

Hi Stephane

 There is not enough information here for me to tell much.  On the second part the clock is tied to gnd. If this is not a mistake then that is the problem.

Also D1 is tied to gnd so even if there is a clock the output will stay low.

If it is just a typo then here are some things to check. be sure that no input pins are floating.  Be sure that the input high and low levels are in spec.

Hi, 

The output 's component is set to "1" at each edge of clock.

But when i put ON the component ,like the connection is on the schematic, the output's state change '0' to '1'.

I think the problem is material because another reference don't make this issue.

I 've realised a lot of test with this component. I've make a test with the Q1 link with GND also it's another output that the state change 0 to 1.

All input are link with GND for the test.

I've make pull down resistance in output.

Hi Stephane

   If this problem happens at power up then this is normal. The output will not be guarranteed until the part gets a rising edge on the clock.

When the part is powered up the outputs will be random until the first clock and then the part will operate normally.

Hi Chris,

I'm OK with what you said.

But I have another 74LS374 with another ref and i don't have this problem.

The subcontractor buy component from TI's Distributor.

As the part is powering it it will set the output accoriding to what it senses internally. This can depend an a very slight process shift that is typical from lot to lot.

You may get one lot that powers up one way and one that poweres up the other. You can not depend on the output until after the first clock.