Logic maximum speed

unai goyarrola

Prodigy 20 points

hello,

I want to use a 74AUP1G125 as a buffer for a 15MHz clock signal. I have seen in the datasheet :

Δt/Δv Input transition rise or fall rate VCC = 0.8 V to 3.6 V 200 ns/V

Does it mean that the maximum frequency, if Vcc=3.3V, is 757KHz?

This is 200ns/V * 3.3V *2(rise+fall)= 1320ns ==> 757KHz

over 12 years ago

0 Chris Cockrill over 12 years ago

TI__Mastermind 46480 points

The Δt/Δv spec is the slowest edge you cand have on the input. Fmax would be determined by the output slew rate.

At 3.3V the max frequency will be about 260Mhz. You should not have any problems running at 15Mhz.

0 unai goyarrola over 12 years ago in reply to Chris Cockrill

Prodigy 20 points

Which is the output slew rate? I cann't find it in the datasheet.

0 Chris Cockrill over 12 years ago in reply to unai goyarrola

TI__Mastermind 46480 points

Output slew is not specd because it will depend on the load. only parts with clocks will have Fmax limits. The best way to get a good indication of Fmax is to look at a part with a clock in the same family. Clocked parts will actually run slightly slower than strait through parts so using the clocked parts Fmax is a safe way to get an Fmax value.

I looked at the SN74AUP1G79 to get the Fmax for your part.

Logic

Logic forum

Logic maximum speed