Dear forum team, can you please respond to the following customer question:
I’m looking into using an SN74CBTLV3257 4 Bit 1-of-2 FET Multiplexer/Demultiplexer in a SPI bus to connect a SPI Flash chip to either (1) an FPGA or (2) intel chipset GPIO pins programmed to behave like a SPI bus. In either scenario, the SPI flash would be the slave device.
GPIO ____
\
MUX ----- SPI FLASH
FPGA ____/
This way we can program the SPI flash from software accessing the GPIO pins, and then allow the FPGA access later. Ideally, it would operate at 33Mhz, however we can slow it down as far as 2MHz if need be.
In any case, I was wondering about the signal integrity of the SPI Clock signal (or even just SPI signals in general) through one of these FET Multiplexers.
We anticipate the bus being quite short, however are curious as to whether the parallel termination on the clock is best used just before the multiplexer or just before the final SPI flash part. My understanding is that this would be best placed just before the SPI Flash (as I presume this is just a switch and not actively driving the signal), however I would like to know if this is really the case and if these multiplexers have any significant impact of signal integrity when used in SPI applications.
Thanks,
Aaron
