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TMS570 - EMIF

Alex Spivak
Intellectual 930 points

I am using the EMIF on TMS570 to access FPGA and SRAM asynchronously in normal, 16 bit mode. It seems like I am able to properly access the SRA, but I have issues with the FPGA and I was examining the write sequence finding a strange bus behavior that I would want to understand. When I write a 32 bit value I see a sequence of three write cycles. Two of the cycles have BHE and BLE low and one has those lines at high. My first question is why there are three write cycles? For two 16 bit words I would expect two writes on the bus. Another thing that I observed is that the upper word is written to a lower address and the lower word to the higher address. For a Big Endian processor I would expect this to be the other way. I don't see endian confusion when writing/reading to/from SRAM programmatically, but I see this anomaly on the bus (EMIF) signals. Can anyone explain?

Thanks,

Alex

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  • 0
    TI__Mastermind 22715 points

    Alex,

    You need to configure R4 MPU to make external memory region as "device" memory. Please refer to TMS570 silicon errata documents for more details.

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    TI__Mastermind 22715 points

    Alex,

    I was told that this requirement is not a part of the errata yet.

    On TMS570, redundant WE pulses are generated when the external memory is configured as "normal" (default). You need to configure the external memory as "device" to eliminate the redundant WE pulses. I would also propose to configure all peripherals as "device" to better utilize CPU. To write to a "device" memory, CPU just needs to write to a CPU store buffer and continue. To write to a "strongly ordered memory" CPU will have to wait for the data reaches the destination. If you want to use memset() to initialize external memory, please make sure that the start address is 64 bit aliened because it uses store multiple instruction (STM).

    Thanks and regards,

    Zhaohong

  • 0 in reply to Zhaohong Zhang
    Intellectual 930 points

    Hi Zhaohong,

    I'm not sure what you are referring to by setting the external memory as "device" instead of normal. In the TRM, Asynchronous Controller and Interface section 17.2.6 there is a Normal mode and Strobe Mode. Can you please tell me in which document and section I can find how to setup the EMIF to "device" mode.

    Regarding the "strongly ordered memory" if I don't use memset can I safely write 32 bit values? Will it always write low word into upper address and high word into lower address, or I can force it otherwise by defining "strongly ordered memory". How do I define "strongly ordered memory"

    Thanks,

    Alex

  • 0 in reply to Alex Spivak
    TI__Mastermind 22715 points

    Alex,

    You need to set up Cortex-R4 MPU for the address ranges of the external memory. Please refer to Cortex-R4 TRM for more details. You should be able to download Cortex R4 TRM from ARM website.

    Thanks and regards,

    Zhaohong